add4.sym

dsch第2版本

USER SYMBOL by DSCH 2.0c
DATE 03/11/99 18:01:35
SYM  #Add4.sym
BB(-10,-10,130,110)
TITLE 10 10  #Add4
MODEL 6000
REC(0,0,120,100)
PIN(-10,40,0.000,0)Y1
PIN(-10,30,0.000,0)Y2
PIN(-10,20,0.000,0)Y3
PIN(-10,10,0.000,0)Y4
PIN(90,110,0.000,0)InitialCarry
PIN(-10,80,0.000,0)X1
PIN(-10,50,0.000,0)X4
PIN(-10,60,0.000,0)X3
PIN(-10,70,0.000,0)X2
PIN(130,40,0.060,0)i0
PIN(130,10,0.060,0)i3
PIN(130,50,0.060,0)Add4Carry
PIN(130,20,0.060,0)i2
PIN(130,30,0.060,0)i1
LIG(-10,40,0,40)
LIG(-10,30,0,30)
LIG(-10,20,0,20)
LIG(-10,10,0,10)
LIG(90,100,90,110)
LIG(-10,80,0,80)
LIG(-10,50,0,50)
LIG(-10,60,0,60)
LIG(-10,70,0,70)
LIG(120,40,130,40)
LIG(120,10,130,10)
LIG(120,50,130,50)
LIG(120,20,130,20)
LIG(120,30,130,30)
LIG(0,0,0,100)
LIG(0,0,120,0)
LIG(120,0,120,100)
LIG(120,100,0,100)
VLG module fadd( C,B,A,Sum,Carry);
VLG   input C,B,A;
VLG   output Sum,Carry;
VLG   wire w1,w2,w3,w4;
VLG   xor xor21(Sum,w1,C);
VLG   xor xor22(w1,A,B);
VLG   nand nand21(w4,B,A);
VLG   nand nand22(w3,B,C);
VLG   nand nand23(w2,A,C);
VLG   nand nand31(Carry,w4,w3,w2);
VLG endmodule
VLG 
VLG module bug( Y1,Y2,Y3,Y4,InitialCarry,X1,X4,X3,
VLG  X2,i0,i3,Add4Carry,i2,i1);
VLG  input Y1,Y2,Y3,Y4,InitialCarry,X1,X4,X3;
VLG  input X2;
VLG  output i0,i3,Add4Carry,i2,i1;
VLG  wire w1,w2,w3,w4,w5,w6,w7,w8;
VLG  wire w9,w10,w11,w12,w13,w14,w15,w16;
VLG  wire w17,w18,w19;
VLG  fadd fadd1( w3,Y3,X3,i2,w2);
VLG  fadd fadd2( w2,Y4,X4,i3,Add4Carry);
VLG  fadd fadd3( InitialCarry,Y1,X1,i0,w1);
VLG  fadd fadd4( w1,Y2,X2,i1,w3);
VLG endmodule
FSYM