fadd.sym

dsch第2版本

USER SYMBOL by DSCH 2.0c
DATE 03/11/99 21:07:31
SYM  #fadd.sym
BB(0,0,30,40)
TITLE 10 10  #fadd
MODEL 6000
REC(5,5,20,30)
PIN(0,10,0.000,0)C
PIN(0,20,0.000,0)B
PIN(0,30,0.000,0)A
PIN(30,10,0.060,0)Sum
PIN(30,20,0.060,0)Carry
LIG(0,10,5,10)
LIG(0,20,5,20)
LIG(0,30,5,30)
LIG(25,10,30,10)
LIG(25,20,30,20)
LIG(5,5,5,35)
LIG(5,5,25,5)
LIG(25,5,25,35)
LIG(25,35,5,35)
VLG module fadd( C,B,A,Sum,Carry);
VLG  input C,B,A;
VLG  output Sum,Carry;
VLG  wire w1,w2,w3,w4,w5,w6;
VLG   xor xor21(Sum,w3,C);
VLG   xor xor22(w3,A,B);
VLG  nand nand21(w6,B,A);
VLG  nand nand22(w5,B,C);
VLG  nand nand23(w4,A,C);
VLG  nand nand31(Carry,w6,w5,w4);
VLG endmodule
FSYM