hppa.h

早期freebsd实现

/* Table of opcodes for the hppa.
   Copyright (C) 1990 Free Software Foundation, Inc.

This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.

GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 1, or (at your option)
any later version.

GAS/GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING.  If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */

/*
   HP PA-RISC support was contributed by the Center for Software Science
   at the University of Utah.
 */

#if !defined(__STDC__) && !defined(const)
#define const
#endif

/*
 * Structure of an opcode table entry.
 */

/* There are two kinds of delay slot nullification: normal which is
 * controled by the nullification bit, and conditional, which depends 
 * on the direction of the branch and its success or failure.
 */
enum delay_type {NONE, NORMAL, CONDITIONAL};
struct pa_opcode
{
    const char *name;
    unsigned long int match;	/* Bits that must be set...  */
    unsigned long int mask;	/* ... in these bits. */
    char *args;
    /* Nonzero if this is a delayed branch instruction.  */
    char delayed;
};

/*
   All hppa opcodes are 32 bits.

   The match component is a mask saying which bits must match a
   particular opcode in order for an instruction to be an instance
   of that opcode.

   The args component is a string containing one character
   for each operand of the instruction.

   Bit positions in this description follow HP usage of lsb = 31,
   "at" is lsb of field.
   
Kinds of operands:
   x    register field at 15.
   b    register field at 10.
   t    register field at 31.
   5    5 bit immediate at 15.
   s    2 bit space specifier at 17.
   S    3 bit space specifier at 18.
   c    indexed load completer.
   C    short load and store completer.
   Y	Store Bytes Short completer
   <    non-negated compare/subtract conditions.
   -	compare/subtract conditions
   +    non-negated add conditions
   &    logical instruction conditions
   U    unit instruction conditions
   >    shift/extract/deposit conditions.
   ~    bvb,bb conditions
   V    5 bit immediate value at 31
   i    11 bit immediate value at 31
   j    14 bit immediate value at 31
   k    21 bit immediate value at 31
   n	nullification for branch instructions
   w    12 bit branch displacement
   W    17 bit branch displacement

Also these (PJH):

   B    either s,b or b where

           s    2 bit space specifier at 17.
           b    register field at 10.

   p    5 bit shift count at 26 (to support the SHD instruction) encoded as
        31-p
   P    5 bit bit position at 26
   T    5 bit field length at 31 (encoded as 32-T)
   A    13 bit immediate at 18 (to support the BREAK instruction)
   Z    System Control Completer (to support LDA, LHA, etc.)
   D    26 bit immediate at 31 (to support the DIAG instruction)

   f    3 bit Special Function Unit identifier at 25
   O    20 bit Special Function Unit operation split between 15 bits at 20
        and 5 bits at 31
   o    15 bit Special Function Unit operation at 20
   2    22 bit Special Function Unit operation split between 17 bits at 20
        and 5 bits at 31
   1    15 bit Special Function Unit operation split between 10 bits at 20
        and 5 bits at 31
   0    10 bit Special Function Unit operation split between 5 bits at 20
        and 5 bits at 31
   u    3 bit coprocessor unit identifier at 25
   F    Source Floating Point Operand Format Completer encoded 2 bits at 20
   G    Destination Floating Point Operand Format Completer encoded 2 bits at 18
   M    Floating-Point Compare Conditions (encoded as 5 bits at 31)
#ifdef GAS
   ?    negated or non-negated compare/subtract conditions
        (used only by 'comb' and 'comib' pseudo-instructions)
   !    negated or non-negated add conditions
        (used only by 'addb' and 'addib' pseudo-instructions)
#else GDB
   ?    negated compare/subtract conditions.
   !    non-negated add conditions.
   @    negated add conditions.
#endif
   r	5 bit immediate value at 31 (for the break instruction)
	(very similar to V above, except the value is unsigned instead of
	low_sign_ext)
   R	5 bit immediate value at 15 (for the ssm, rsm instruction)
	(same as r above, except the value is in a different location)
   Q	5 bit immediate value at 10 (a bit position specified in
	the bb instruction. It's the same as r above, except the
        value is in a different location)

And these (PJH) for PA-89 F.P. registers and instructions:

   v    a 't' operand type extended to handle L/R register halves.
   E    a 'b' operand type extended to handle L/R register halves.
   X    an 'x' operand type extended to handle L/R register halves.
   4    a variation of the 'b' operand type for 'fmpyadd' and 'fmpysub'
   6    a variation of the 'x' operand type for 'fmpyadd' and 'fmpysub'
   7    a variation of the 't' operand type for 'fmpyadd' and 'fmpysub'
   8    5 bit register field at 20 (used in 'fmpyadd' and 'fmpysub')
   9    5 bit register field at 25 (used in 'fmpyadd' and 'fmpysub')
   H    Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
        (very similar to 'F')

*/

/* The order of the opcodes in this table is significant:
   
   * The assembler requires that all instances of the same mnemonic must be
   consecutive.  If they aren't, the assembler will bomb at runtime.

   * The disassembler should not care about the order of the opcodes.  */

static struct pa_opcode pa_opcodes[] =
{

{ "ldw",        0x48000000, 0xfc000000, "j(B),x"},
{ "ldh",        0x44000000, 0xfc000000, "j(B),x"},
{ "ldb",        0x40000000, 0xfc000000, "j(B),x"},
{ "stw",        0x68000000, 0xfc000000, "x,j(B)"},
{ "sth",        0x64000000, 0xfc000000, "x,j(B)"},
{ "stb",        0x60000000, 0xfc000000, "x,j(B)"},
{ "ldwm",       0x4c000000, 0xfc000000, "j(B),x"},
{ "stwm",       0x6c000000, 0xfc000000, "x,j(B)"},
{ "ldwx",       0x0c000080, 0xfc001fc0, "cx(B),t"},
{ "ldhx",       0x0c000040, 0xfc001fc0, "cx(B),t"},
{ "ldbx",       0x0c000000, 0xfc001fc0, "cx(B),t"},
{ "ldwax",      0x0c000180, 0xfc00dfc0, "cx(b),t"},
{ "ldcwx",      0x0c0001c0, 0xfc001fc0, "cx(B),t"},
{ "ldws",	0x0c001080, 0xfc001fc0, "C5(B),t"},
{ "ldhs",	0x0c001040, 0xfc001fc0, "C5(B),t"},
{ "ldbs",	0x0c001000, 0xfc001fc0, "C5(B),t"},
{ "ldwas",	0x0c001180, 0xfc00dfc0, "C5(b),t"},
{ "ldcws",	0x0c0011c0, 0xfc001fc0, "C5(B),t"},
{ "stws",	0x0c001280, 0xfc001fc0, "Cx,V(B)"},
{ "sths",	0x0c001240, 0xfc001fc0, "Cx,V(B)"},