m88k.h

早期freebsd实现

# define sf7m  11
# define sf6m  10
# define sf5m   9
# define sf4m   8
# define sf3m   7
# define sf2m   6
# define sf1m   5
# define mam    4
# define inm    3
# define exm    2
# define trm    1
# define ovfm   0

#define	    MODEMASK   (1<<(mode-1))
# define    SILENT     0   /* simulate without output to crt */
# define    VERBOSE    1   /* simulate in verbose mode */
# define    PR_INSTR   2   /* only print instructions */

# define    RESET      16 /* reset phase */

# define    PHASE1     0  /* data path phases */
# define    PHASE2     1

/* the 1 clock operations */

# define    ADDU        1
# define    ADDC        2
# define    ADDUC       3
# define    ADD         4

# define    SUBU    ADD+1
# define    SUBB    ADD+2
# define    SUBUB   ADD+3
# define    SUB     ADD+4

# define    AND     ADD+5
# define    OR      ADD+6
# define    XOR     ADD+7
# define    CMP     ADD+8
                        
/* the LOADS */

# define    LDAB    CMP+1
# define    LDAH    CMP+2
# define    LDA     CMP+3
# define    LDAD    CMP+4

# define    LDB   LDAD+1
# define    LDH   LDAD+2
# define    LD    LDAD+3
# define    LDD   LDAD+4
# define    LDBU  LDAD+5
# define    LDHU  LDAD+6

/* the STORES */

# define    STB    LDHU+1
# define    STH    LDHU+2
# define    ST     LDHU+3
# define    STD    LDHU+4

/* the exchange */

# define    XMEMBU LDHU+5
# define    XMEM   LDHU+6

/* the branches */
# define    JSR    STD+1
# define    BSR    STD+2
# define    BR     STD+3
# define    JMP    STD+4
# define    BB1    STD+5
# define    BB0    STD+6
# define    RTN    STD+7
# define    BCND   STD+8

/* the TRAPS */
# define    TB1    BCND+1
# define    TB0    BCND+2
# define    TCND   BCND+3
# define    RTE    BCND+4
# define    TBND   BCND+5

/* the MISC instructions */
# define    MUL     TBND + 1
# define    DIV     MUL  +2
# define    DIVU    MUL  +3
# define    MASK    MUL  +4
# define    FF0     MUL  +5
# define    FF1     MUL  +6
# define    CLR     MUL  +7
# define    SET     MUL  +8
# define    EXT     MUL  +9
# define    EXTU    MUL  +10
# define    MAK     MUL  +11
# define    ROT     MUL  +12

/* control register manipulations */

# define    LDCR    ROT  +1
# define    STCR    ROT  +2
# define    XCR     ROT  +3

# define    FLDCR    ROT  +4
# define    FSTCR    ROT  +5
# define    FXCR     ROT  +6


# define    NOP     XCR +1

/* floating point instructions */

# define    FADD    NOP +1
# define    FSUB    NOP +2
# define    FMUL    NOP +3
# define    FDIV    NOP +4
# define    FSQRT   NOP +5
# define    FCMP    NOP +6
# define    FIP     NOP +7
# define    FLT     NOP +8
# define    INT     NOP +9
# define    NINT    NOP +10
# define    TRNC    NOP +11
# define    FLDC   NOP +12
# define    FSTC   NOP +13
# define    FXC    NOP +14

# define UEXT(src,off,wid) ((((unsigned int)(src))>>(off)) & ((1<<(wid)) - 1))
# define SEXT(src,off,wid) (((((int)(src))<<(32-((off)+(wid)))) >>(32-(wid))) )
# define MAKE(src,off,wid) \
  ((((unsigned int)(src)) & ((1<<(wid)) - 1)) << (off))

# define opword(n) (unsigned long) (memaddr->mem.l)

/*  Constants and Masks */

#define SFU0       0x80000000
#define SFU1       0x84000000
#define SFU7       0x9c000000
#define RRI10      0xf0000000
#define RRR        0xf4000000
#define SFUMASK    0xfc00ffe0
#define RRRMASK    0xfc00ffe0
#define RRI10MASK  0xfc00fc00
#define DEFMASK    0xfc000000
#define CTRL       0x0000f000
#define CTRLMASK   0xfc00f800

/* Operands types */

#define HEX          1
#define REG          2
#define IND          3
#define CONT         3
#define IND          3
#define BF           4
#define REGSC        5    /* scaled register */
#define CRREG        6    /* control register */
#define FCRREG       7    /* floating point control register */
#define PCREL	     8
#define CONDMASK     9

/* Hashing Specification */

#define HASHVAL     79

/* Type definitions */

typedef unsigned int UINT;

/* Structure templates */

typedef struct {
   unsigned int offset:5;
   unsigned int width:6;
   unsigned int type:5;
} OPSPEC;

	struct SIM_FLAGS {
	      int  ltncy,   /* latency (max number of clocks needed to execute) */
		  extime,   /* execution time (min number of clocks needed to execute) */
		  wb_pri;   /* writeback slot priority */
   unsigned long   op:OP,   /* simulator version of opcode */
	     imm_flags:2,   /* 10,16 or 26 bit immediate flags */
	      rs1_used:1,   /* register source 1 used */
	      rs2_used:1,   /* register source 2 used */
	      rsd_used:1,   /* register source/dest used */
		c_flag:1,   /* complement */
		u_flag:1,   /* upper half word */
		n_flag:1,   /* execute next */
	       wb_flag:1,   /* uses writeback slot */
	       dest_64:1,   /* double precision dest */
		 s1_64:1,   /* double precision source 1 */
		 s2_64:1,   /* double precision source 2 */
	    scale_flag:1;   /* register is scaled */
};