rtl.def

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/* This file contains the definitions and documentation for the
   Register Transfer Expressions (rtx's) that make up the
   Register Transfer Language (rtl) used in the Back End of the GNU compiler.
   Copyright (C) 1987-1991 Free Software Foundation, Inc.

This file is part of GNU CC.

GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING.  If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */


/* Expression definitions and descriptions for all targets are in this file.
   Some will not be used for some targets.

   The fields in the cpp macro call "DEF_RTL_EXPR()"
   are used to create declarations in the C source of the compiler.

   The fields are:

   1.  The internal name of the rtx used in the C source.
   It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
   By convention these are in UPPER_CASE.

   2.  The name of the rtx in the external ASCII format read by
   read_rtx(), and printed by print_rtx().
   These names are stored in rtx_name[].
   By convention these are the internal (field 1) names in lower_case.

   3.  The print format, and type of each rtx->fld[] (field) in this rtx.
   These formats are stored in rtx_format[].
   The meaning of the formats is documented in front of this array in rtl.c
   
   4.  The class of the rtx.  These are stored in rtx_class and are accessed
   via the GET_RTX_CLASS macro.  They are defined as follows:

     "o" an rtx code that can be used to represent an object (e.g, REG, MEM)
     "<" an rtx code for a comparison (e.g, EQ, NE, LT)
     "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
     "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
     "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
     "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
     "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
     "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
     "m" an rtx code for something that matches in insns (e.g, MATCH_DUP)
     "x" everything else
     
   */

/* ---------------------------------------------------------------------
   Expressions (and "meta" expressions) used for structuring the
   rtl representation of a program.
   --------------------------------------------------------------------- */

/* an expression code name unknown to the reader */
DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x')

/* (NIL) is used by rtl reader and printer to represent a null pointer.  */

DEF_RTL_EXPR(NIL, "nil", "*", 'x')

/* ---------------------------------------------------------------------
   Expressions used in constructing lists.
   --------------------------------------------------------------------- */

/* a linked list of expressions */
DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x')

/* a linked list of instructions.
   The insns are represented in print by their uids.  */
DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x')

/* ----------------------------------------------------------------------
   Expression types for machine descriptions.
   These do not appear in actual rtl code in the compiler.
   ---------------------------------------------------------------------- */

/* Appears only in machine descriptions.
   Means use the function named by the second arg (the string)
   as a predicate; if matched, store the structure that was matched
   in the operand table at index specified by the first arg (the integer).
   If the second arg is the null string, the structure is just stored.

   A third string argument indicates to the register allocator restrictions
   on where the operand can be allocated.

   If the target needs no restriction on any instruction this field should
   be the null string.

   The string is prepended by:
   '=' to indicate the operand is only written to.
   '+' to indicate the operand is both read and written to.

   Each character in the string represents an allocatable class for an operand.
   'g' indicates the operand can be any valid class.
   'i' indicates the operand can be immediate (in the instruction) data.
   'r' indicates the operand can be in a register.
   'm' indicates the operand can be in memory.
   'o' a subset of the 'm' class.  Those memory addressing modes that
       can be offset at compile time (have a constant added to them).

   Other characters indicate target dependent operand classes and
   are described in each target's machine description.

   For instructions with more than one operand, sets of classes can be
   separated by a comma to indicate the appropriate multi-operand constraints.
   There must be a 1 to 1 correspondence between these sets of classes in
   all operands for an instruction.
   */
DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm')

/* Appears only in machine descriptions.
   Means match a SCRATCH or a register.  When used to generate rtl, a
   SCRATCH is generated.  As for MATCH_OPERAND, the mode specifies
   the desired mode and the first argument is the operand number.
   The second argument is the constraint.  */
DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm')

/* Appears only in machine descriptions.
   Means match only something equal to what is stored in the operand table
   at the index specified by the argument.  */
DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm')

/* Appears only in machine descriptions.
   Means apply a predicate, AND match recursively the operands of the rtx.
   Operand 0 is the operand-number, as in match_operand.
   Operand 1 is a predicate to apply (as a string, a function name).
   Operand 2 is a vector of expressions, each of which must match
   one subexpression of the rtx this construct is matching.  */
DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm')

/* Appears only in machine descriptions.
   Means to match a PARALLEL of arbitrary length.  The predicate is applied
   to the PARALLEL and the initial expressions in the PARALLEL are matched.
   Operand 0 is the operand-number, as in match_operand.
   Operand 1 is a predicate to apply to the PARALLEL.
   Operand 2 is a vector of expressions, each of which must match the 
   corresponding element in the PARALLEL.  */
DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm')

/* Appears only in machine descriptions.
   Means match only something equal to what is stored in the operand table
   at the index specified by the argument.  For MATCH_OPERATOR.  */
DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm')

/* Appears only in machine descriptions.
   Means match only something equal to what is stored in the operand table
   at the index specified by the argument.  For MATCH_PARALLEL.  */
DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm')

/* Appears only in machine descriptions.
   Defines the pattern for one kind of instruction.
   Operand:
   0: names this instruction.
      If the name is the null string, the instruction is in the
      machine description just to be recognized, and will never be emitted by
      the tree to rtl expander.
   1: is the pattern.
   2: is a string which is a C expression
      giving an additional condition for recognizing this pattern.
      A null string means no extra condition.
   3: is the action to execute if this pattern is matched.
      If this assembler code template starts with a * then it is a fragment of
      C code to run to decide on a template to use.  Otherwise, it is the
      template to use.
   4: optionally, a vector of attributes for this insn.
     */
DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEssV", 'x')

/* Definition of a peephole optimization.
   1st operand: vector of insn patterns to match
   2nd operand: C expression that must be true
   3rd operand: template or C code to produce assembler output.
   4: optionally, a vector of attributes for this insn.
     */
DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EssV", 'x')

/* Definition of a split operation.
   1st operand: insn pattern to match
   2nd operand: C expression that must be true
   3rd operand: vector of insn patterns to place into a SEQUENCE
   4th operand: optionally, some C code to execute before generating the
	insns.  This might, for example, create some RTX's and store them in
	elements of `recog_operand' for use by the vector of insn-patterns.
	(`operands' is an alias here for `recog_operand').   */
DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x')

/* Definition of a combiner pattern.
   Operands not defined yet.  */
DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x')

/* Define how to generate multiple insns for a standard insn name.
   1st operand: the insn name.
   2nd operand: vector of insn-patterns.
	Use match_operand to substitute an element of `recog_operand'.
   3rd operand: C expression that must be true for this to be available.
	This may not test any operands.
   4th operand: Extra C code to execute before generating the insns.
	This might, for example, create some RTX's and store them in
	elements of `recog_operand' for use by the vector of insn-patterns.
	(`operands' is an alias here for `recog_operand').  */
DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x')
   
/* Define a requirement for delay slots.
   1st operand: Condition involving insn attributes that, if true,
	        indicates that the insn requires the number of delay slots
		shown.
   2nd operand: Vector whose length is the three times the number of delay
		slots required.
	        Each entry gives three conditions, each involving attributes.
		The first must be true for an insn to occupy that delay slot
		location.  The second is true for all insns that can be
		annulled if the branch is true and the third is true for all
		insns that can be annulled if the branch is false. 

   Multiple DEFINE_DELAYs may be present.  They indicate differing
   requirements for delay slots.  */
DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x')

/* Define a set of insns that requires a function unit.  This means that
   these insns produce their result after a delay and that there may be
   restrictions on the number of insns of this type that can be scheduled
   simultaneously.

   More than one DEFINE_FUNCTION_UNIT can be specified for a function unit.
   Each gives a set of operations and associated delays.  The first three
   operands must be the same for each operation for the same function unit.

   All delays are specified in cycles.

   1st operand: Name of function unit (mostly for documentation)
   2nd operand: Number of identical function units in CPU
   3rd operand: Total number of simultaneous insns that can execute on this
		function unit; 0 if unlimited.
   4th operand: Condition involving insn attribute, that, if true, specifies
		those insns that this expression applies to.
   5th operand: Constant delay after which insn result will be
		available.
   6th operand: Delay until next insn can be scheduled on the function unit
		executing this operation.  The meaning depends on whether or
		not the next operand is supplied.