arm.h

早期freebsd实现

/* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
   Copyright (C) 1991 Free Software Foundation, Inc.
   Contributed by Pieter `Tiggr' Schoenmakers ([e-mail])
              and Martin Simmons (@harleqn.co.uk).

This file is part of GNU CC.

GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING.  If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */

/* Sometimes the directive `riscos' is checked.  This does not imply that this
   tm file can be used unchanged to build a GCC for RISC OS.
   (Since in fact, it can't.)  */

extern void output_prologue ();
extern void output_epilogue ();
extern char *arm_output_asm_insn ();
extern char *arm_output_llc ();
extern char *output_add_immediate ();
extern char *output_call ();
extern char *output_move_double ();
extern char *output_mov_double_fpu_from_arm ();
extern char *output_mov_double_arm_from_fpu ();
extern char *output_mov_immediate ();
extern char *output_multi_immediate ();
extern char *output_shifted_move ();

/* Translation to find startup files.  On RISCiX boxes, gcrt0.o is in
   /usr/lib.  */
#define STARTFILE_SPEC  \
  "%{pg:/usr/lib/gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"

#ifdef riscos
#define CPP_PREDEFINES  "-Darm -Driscos"
#else
#define CPP_PREDEFINES  "-Darm -Driscix -Dunix"
#endif

/* Run-time Target Specification.  */
#define TARGET_VERSION  \
  fputs (" (ARM/RISCiX)", stderr);

/* Run-time compilation parameters selecting different hardware subsets.
   On the ARM, misuse it in a different way.  */
extern int target_flags;

/* Nonzero if the function prologue (and epilogue) should obey
   the ARM Procedure Call Standard.  */
#define TARGET_APCS	(target_flags & 1)

/* Nonzero if the function prologue should output the function name to enable
   the post mortem debugger to print a backtrace (very useful on RISCOS,
   unused on RISCiX).  Specifying this flag also enables -mapcs.
   XXX Must still be implemented in the prologue.  */
#define TARGET_POKE_FUNCTION_NAME	(target_flags & 2)

/* Nonzero if floating point instructions are emulated by the FPE, in which
   case instruction scheduling becomes very uninteresting.  */
#define TARGET_FPE	(target_flags & 4)

#define TARGET_SWITCHES  \
{                         			\
  {"apcs",		 1},			\
  {"poke-function-name", 2},			\
  {"fpe",		 4},			\
  {"",   		 TARGET_DEFAULT }	\
}

#define TARGET_DEFAULT  0

#define TARGET_MEM_FUNCTIONS 1

/* OVERRIDE_OPTIONS takes care of the following:
   - if -mpoke-function-name, then -mapcs.
   - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name.
   - if floating point is done by emulation, forget about instruction
     scheduling.  Note that this only saves compilation time; it doesn't
     matter for the final code.  */
#ifdef riscos
#define TARGET_WHEN_DEBUGGING  3
#else
#define TARGET_WHEN_DEBUGGING  1
#endif

#define OVERRIDE_OPTIONS  \
{								\
  if (write_symbols != NO_DEBUG)				\
    target_flags |= TARGET_WHEN_DEBUGGING;			\
  else if (TARGET_POKE_FUNCTION_NAME)				\
    target_flags |= 1;						\
  if (TARGET_FPE)						\
    flag_schedule_insns = flag_schedule_insns_after_reload = 0;	\
}

/* Omitting the frame pointer is a very good idea on the ARM, especially if
   not TARGET_APCS, in which case all that pushing on function entry isn't
   mandatory anymore.  */
#define OPTIMIZATION_OPTIONS(OPTIMIZE)  \
{					\
  if (OPTIMIZE)				\
    flag_omit_frame_pointer = 1;	\
}

/* Target machine storage Layout.  */

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.  */
#define BITS_BIG_ENDIAN  0

/* Define this if most significant byte of a word is the lowest numbered.  */
#define BYTES_BIG_ENDIAN  0

/* Define this if most significant word of a multiword number is the lowest
   numbered.  */
#define WORDS_BIG_ENDIAN  0

/* Number of bits in an addressable storage unit */
#define BITS_PER_UNIT  8

#define BITS_PER_WORD  32

#define UNITS_PER_WORD	4

#define POINTER_SIZE  32

#define PARM_BOUNDARY  	32

#define STACK_BOUNDARY  32

#define FUNCTION_BOUNDARY  32

#define EMPTY_FIELD_BOUNDARY  32

#define BIGGEST_ALIGNMENT  32

/* Every structures size must be a multiple of 32 bits.  */
#define STRUCTURE_SIZE_BOUNDARY 32

#define STRICT_ALIGNMENT 1

/* Define number of bits in most basic integer type.
   (If undefined, default is BITS_PER_WORD).  */
/* #define INT_TYPE_SIZE */

/* Standard register usage.  */

/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
   (S - saved over call).

	r0	   *	argument word/integer result
	r1-r3		argument word

	r4-r8	     S	register variable
	r9	     S	(rfp) register variable (real frame pointer)

	r10  	   F S	(sl) stack limit (not currently used)
	r11 	   F S	(fp) argument pointer
	r12		(ip) temp workspace
	r13  	   F S	(sp) lower end of current stack frame
	r14		(lr) link address/workspace
	r15	   F	(pc) program counter

	f0		floating point result
	f1-f3		floating point scratch

	f4-f7	     S	floating point variable

   *: See CONDITIONAL_REGISTER_USAGE  */

/* The number of hard registers is 16 ARM + 8 FPU.  */
#define FIRST_PSEUDO_REGISTER  24

/* 1 for registers that have pervasive standard uses
   and are not available for the register allocator.  */
#define FIXED_REGISTERS  \
{                        \
  0,0,0,0,0,0,0,0,	 \
  0,0,1,1,0,1,0,1,	 \
  0,0,0,0,0,0,0,0	 \
}

/* 1 for registers not available across function calls.
   These must include the FIXED_REGISTERS and also any
   registers that can be used without being saved.
   The latter must include the registers where values are returned
   and the register where structure-value addresses are passed.
   Aside from that, you can include as many other registers as you like.  */
#define CALL_USED_REGISTERS  \
{                            \
  1,1,1,1,0,0,0,0,	     \
  0,0,1,1,1,1,1,1,	     \
  1,1,1,1,0,0,0,0	     \
}

/* If doing stupid life analysis, avoid a bug causing a return value r0 to be
   trampled.  This effectively reduces the number of available registers by 1.
   XXX It is a hack, I know.
   XXX Is this still needed?  */
#define CONDITIONAL_REGISTER_USAGE  \
{			\
  if (obey_regdecls)	\
    fixed_regs[0] = 1;	\
}

/* Return number of consecutive hard regs needed starting at reg REGNO
   to hold something of mode MODE.
   This is ordinarily the length in words of a value of mode MODE
   but can be less for certain modes in special long registers.

   On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
   mode.  */
#define HARD_REGNO_NREGS(REGNO, MODE)  \
    ((REGNO) >= 16 ? 1							\
     : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
   This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
   regs holding FP.  */
#define HARD_REGNO_MODE_OK(REGNO, MODE)  \
  ((REGNO) < 16 || GET_MODE_CLASS (MODE) == MODE_FLOAT)

/* Value is 1 if it is a good idea to tie two pseudo registers
   when one has mode MODE1 and one has mode MODE2.
   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
   for any hard reg, then this must be 0 for correct output.  */
#define MODES_TIEABLE_P(MODE1, MODE2)  \
  (((MODE1) == SFmode || (MODE1) == DFmode)      \
   == ((MODE2) == SFmode || (MODE2) == DFmode))

/* Specify the registers used for certain standard purposes.
   The values of these macros are register numbers.  */

/* Define this if the program counter is overloaded on a register.  */
#define PC_REGNUM		15

/* Register to use for pushing function arguments.  */
#define STACK_POINTER_REGNUM	13

/* Base register for access to local variables of the function.  */
#define FRAME_POINTER_REGNUM	9

/* Value should be nonzero if functions must have frame pointers.
   Zero means the frame pointer need not be set up (and parms may be accessed
   via the stack pointer) in functions that seem suitable.  */
#define FRAME_POINTER_REQUIRED	0

/* Base register for access to arguments of the function.  */
#define ARG_POINTER_REGNUM	11

/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
   as an invisible last argument (possible since varargs don't exist in
   Pascal), so the following is not true.  */
#define STATIC_CHAIN_REGNUM	8

/* Register in which address to store a structure value
   is passed to a function.  */
#define STRUCT_VALUE_REGNUM	0

/* The order in which register should be allocated.  It is good to use ip
   since no saving is required (though calls clobber it).  It is quite good to
   use lr since other calls may clobber it anyway.  */
#define REG_ALLOC_ORDER  \
{                                   \
    0, 1, 2, 3, 12, 14,	4, 5,       \
    6, 7, 8, 10, 9, 11, 13, 15,     \
    16, 17, 18, 19, 20, 21, 22, 23  \
}

/* Register and constant classes.  */

/* Register classes: all ARM regs or all FPU regs---simple! */
enum reg_class
{
  NO_REGS,
  FPU_REGS,
  GENERAL_REGS,
  ALL_REGS,
  LIM_REG_CLASSES
};

#define N_REG_CLASSES  (int) LIM_REG_CLASSES

/* Give names of register classes as strings for dump file.   */
#define REG_CLASS_NAMES  \
{			\
  "NO_REGS",		\
  "FPU_REGS",		\
  "GENERAL_REGS",	\
  "ALL_REGS",		\
}

/* Define which registers fit in which classes.
   This is an initializer for a vector of HARD_REG_SET
   of length N_REG_CLASSES.  */
#define REG_CLASS_CONTENTS  \
{				\
  0x000000,  /* NO_REGS  */	\
  0xFF0000,  /* FPU_REGS */	\
  0x00FFFF,  /* GENERAL_REGS */	\
  0xFFFFFF   /* ALL_REGS */	\
}

/* The same information, inverted:
   Return the class number of the smallest class containing
   reg number REGNO.  This could be a conditional expression
   or could index an array.  */
#define REGNO_REG_CLASS(REGNO)  \
  ((REGNO) < 16 ? GENERAL_REGS : FPU_REGS)

/* The class value for index registers, and the one for base regs.  */
#define INDEX_REG_CLASS  GENERAL_REGS
#define BASE_REG_CLASS	GENERAL_REGS

/* Get reg_class from a letter such as appears in the machine description.
   We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS).  */
#define REG_CLASS_FROM_LETTER(C)  \
  ((C)=='f' ? FPU_REGS : NO_REGS)