📄 pa.h
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/* Definitions of target machine for GNU compiler, for the HP Spectrum. Copyright (C) 1992 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@mcc.com) and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for Software Science at the University of Utah.This file is part of GNU CC.GNU CC is free software; you can redistribute it and/or modifyit under the terms of the GNU General Public License as published bythe Free Software Foundation; either version 1, or (at your option)any later version.GNU CC is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the implied warranty ofMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See theGNU General Public License for more details.You should have received a copy of the GNU General Public Licensealong with GNU CC; see the file COPYING. If not, write tothe Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */enum cmp_type /* comparison type */{ CMP_SI, /* compare integers */ CMP_SF, /* compare single precision floats */ CMP_DF, /* compare double precision floats */ CMP_MAX /* max comparison type */};/* Print subsidiary information on the compiler version in use. */#define TARGET_VERSION fprintf (stderr, " (hppa)");/* Run-time compilation parameters selecting different hardware subsets. */extern int target_flags;/* compile code for HP-PA 1.1 ("Snake") */#define TARGET_SNAKE (target_flags & 1)/* Force gcc not to use the bss segment. This is (temporarily) provided for sites which are using pa-gas-1.36 versions prior to Aug 7, 1992. */#define TARGET_NO_BSS (target_flags & 2)/* Force gcc to only use instructions which are safe when compiling kernels. Specifically, avoid using add instructions with dp (r27) as an argument. Use addil instructions instead. Doing so avoids a nasty bug in the HPUX linker. When HP fixes their linker take this option out. */#define TARGET_KERNEL (target_flags & 4)/* Generate code that will link against HPUX 8.0 shared libraries. Older linkers and assemblers might not support this. */#define TARGET_SHARED_LIBS (target_flags & 8)/* Force all function calls to indirect addressing via a register. This avoids lossage when the function is very far away from the current PC. ??? What about simple jumps, they can suffer from the same problem. Would require significant surgery in pa.md. */#define TARGET_LONG_CALLS (target_flags & 16)/* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits to set or minus the bits to clear. An empty string NAME is used to identify the default VALUE. */#define TARGET_SWITCHES \ {{"snake", 1}, \ {"nosnake", -1}, \ {"pa-risc-1-0", -1}, \ {"pa-risc-1-1", 1}, \ {"no-bss", 2}, \ {"kernel", 4}, \ {"shared-libs", 8}, \ {"no-shared-libs", -8},\ {"long-calls", 16}, \ { "", TARGET_DEFAULT}}#ifndef TARGET_DEFAULT#define TARGET_DEFAULT 0#endif#define DBX_DEBUGGING_INFO#define DEFAULT_GDB_EXTENSIONS 0#if (TARGET_DEFAULT & 1) == 0#define CPP_SPEC "%{msnake:-D__hp9000s700 -D_PA_RISC1_1}\ %{mpa-risc-1-1:-D__hp9000s700 -D_PA_RISC1_1}"#else#define CPP_SPEC "%{!mpa-risc-1-0:-D__hp9000s700 -D_PA_RISC1_1}\ %{!mnosnake:-D__hp9000s700 -D_PA_RISC1_1}"#endif/* Defines for a K&R CC */#ifdef OLD_CC#define CPP_SPEC "%{!gnu:-nostdinc %{!nostinc:-I/usr/include}} \ %{gnu:%{nostdinc}} %{!gnu:-traditional} -Dvolatile=__volatile"#define CC1_SPEC "%{!gnu:-traditional -fwritable-strings -fno-defer-pop} \ %{pg:} %{p:}"#else#define CC1_SPEC "%{pg:} %{p:}"#endif #define LINK_SPEC "-u main"/* Make gcc agree with <machine/ansi.h> */#define SIZE_TYPE "unsigned int"#define PTRDIFF_TYPE "int"#define WCHAR_TYPE "short unsigned int"#define WCHAR_TYPE_SIZE 16/* Omit frame pointer at high optimization levels. */ #define OPTIMIZATION_OPTIONS(OPTIMIZE) \{ \ if (OPTIMIZE >= 2) \ flag_omit_frame_pointer = 1; \}/* Names to predefine in the preprocessor for this target machine. */#define CPP_PREDEFINES "-Dhppa -Dhp9000s800 -D__hp9000s800 -Dhp9k8 -Dunix -D_HPUX_SOURCE -Dhp9000 -Dhp800 -Dspectrum -DREVARGV"/* target machine storage layout *//* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. */#define BITS_BIG_ENDIAN 1/* Define this if most significant byte of a word is the lowest numbered. *//* That is true on the HP-PA. */#define BYTES_BIG_ENDIAN 1/* Define this if most significant word of a multiword number is lowest numbered. *//* For the HP-PA we can decide arbitrarily since there are no machine instructions for them. */#define WORDS_BIG_ENDIAN 1/* number of bits in an addressable storage unit */#define BITS_PER_UNIT 8/* Width in bits of a "word", which is the contents of a machine register. Note that this is not necessarily the width of data type `int'; if using 16-bit ints on a 68000, this would still be 32. But on a machine with 16-bit registers, this would be 16. */#define BITS_PER_WORD 32/* Width of a word, in units (bytes). */#define UNITS_PER_WORD 4/* Width in bits of a pointer. See also the macro `Pmode' defined below. */#define POINTER_SIZE 32/* Allocation boundary (in *bits*) for storing arguments in argument list. */#define PARM_BOUNDARY 32/* Largest alignment required for any stack parameter, in bits. Don't define this if it is equal to PARM_BOUNDARY */#define MAX_PARM_BOUNDARY 64/* Boundary (in *bits*) on which stack pointer should be aligned. */#define STACK_BOUNDARY (TARGET_SNAKE ? 512 : 64)/* Allocation boundary (in *bits*) for the code of a function. */#define FUNCTION_BOUNDARY 32/* Alignment of field after `int : 0' in a structure. */#define EMPTY_FIELD_BOUNDARY 32/* Every structure's size must be a multiple of this. */#define STRUCTURE_SIZE_BOUNDARY 8/* A bitfield declared as `int' forces `int' alignment for the struct. */#define PCC_BITFIELD_TYPE_MATTERS 1/* No data type wants to be aligned rounder than this. */#define BIGGEST_ALIGNMENT 64/* Get around hp-ux assembler bug, and make strcpy of constants fast. */#define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \ ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN))/* Make arrays of chars word-aligned for the same reasons. */#define DATA_ALIGNMENT(TYPE, ALIGN) \ (TREE_CODE (TYPE) == ARRAY_TYPE \ && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))/* Set this nonzero if move instructions will actually fail to work when given unaligned data. */#define STRICT_ALIGNMENT 1/* Generate calls to memcpy, memcmp and memset. */#define TARGET_MEM_FUNCTIONS/* Standard register usage. *//* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. HP-PA 1.0 has 32 fullword registers and 16 floating point registers. The floating point registers hold either word or double word values. 16 additional registers are reserved. HP-PA 1.1 has 32 fullword registers and 32 floating point registers. However, the floating point registers behave differently: the left and right halves of registers are addressable as 32 bit registers. So, we will set things up like the 68k which has different fp units: define separate register sets for the 1.0 and 1.1 fp units. */#define FIRST_PSEUDO_REGISTER 113 /* 32 + 16 1.0 regs + 64 1.1 regs + */ /* 1 shift reg *//* 1 for registers that have pervasive standard uses and are not available for the register allocator. On the HP-PA, these are: Reg 0 = 0 (hardware). However, 0 is used for condition code, so is not fixed. Reg 1 = ADDIL target/Temporary (hardware). Reg 2 = Return Pointer Reg 3 = Unused Reg 4 = Frame Pointer (Gnu) Reg 5-18 = Preserved Registers Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme. Reg 20-22 = Temporary Registers Reg 23-26 = Temporary/Parameter Registers Reg 27 = Global Data Pointer (hp) Reg 28 = Temporary/???/Return Value register Reg 29 = Temporary/Static Chain/Return Value register Reg 30 = stack pointer Reg 31 = Temporary/Millicode Return Pointer (hp) Freg 0-3 = Status Registers Freg 4-7 = Arguments/Return Value Freg 8-11 = Temporary Registers Freg 12-15 = Preserved Registers Freg 16-31 = Reserved On the Snake, fp regs are Freg 0-3 = Status Registers Freg 4L-7R = Arguments/Return Value Freg 8L-11R = Temporary Registers Freg 12L-15R = Preserved Registers Freg 16L-31R = ?? Some partition of temporary and preserved; assume preserved for now. */#define FIXED_REGISTERS \ {0, 0, 1, 1, 1, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 1, 0, 0, 1, 1, \ /* 1.0 fp registers */ \ 1, 1, 1, 1, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ /* 1.1 fp registers */ \ 1, 1, 1, 1, 1, 1, 1, 1, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 1}/* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. */#define CALL_USED_REGISTERS \ {1, 1, 1, 1, 1, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \ /* 1.0 fp registers */ \ 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 0, 0, 0, 0, \ /* 1.1 fp registers */ \ 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \ 1} /* Make sure everything's fine if we *don't* have a given processor. This assumes that putting a register in fixed_regs will keep the compiler's mitts completely off it. We don't bother to zero it out of register classes. Make register 27 global for now. We'll undo this kludge after 2.1. */#define CONDITIONAL_REGISTER_USAGE \{ \ int i; \ HARD_REG_SET x; \ global_regs[27] = 1; \ if (!TARGET_SNAKE) \ { \ COPY_HARD_REG_SET (x, reg_class_contents[(int)SNAKE_FP_REGS]);\ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ if (TEST_HARD_REG_BIT (x, i)) \ fixed_regs[i] = call_used_regs[i] = 1; \ } \ else \ { \ COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ if (TEST_HARD_REG_BIT (x, i)) \ fixed_regs[i] = call_used_regs[i] = 1; \ } \}/* Allocated the call used registers first. This should minimize the number of registers that need to be saved (as call used registers will generally not be allocated across a call). It is possible that it would be wise to allocate the floating point registers before the regular ones, but I doubt it matters. Same comment for parameters versus normal. */#define REG_ALLOC_ORDER \ {19, 20, 21, 22, 23, 24, 25, 26, \ 27, 28, 29, 30, 31, 40, 41, 42, \ 43, 36, 37, 38, 39, \
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