romp.md

早期freebsd实现

{
  if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
    abort();

  operands[0] = XEXP (operands[0], 0);
  if (GET_CODE (operands[0]) == SYMBOL_REF)
    {
      extern rtx get_symref ();
      char *real_fcnname =
		(char *) alloca (strlen (XSTR (operands[0], 0)) + 2);

      /* Copy the data area address to r0.  */
      emit_move_insn (gen_rtx (REG, SImode, 0),
		      force_reg (SImode, operands[0]));
      strcpy (real_fcnname, \".\");
      strcat (real_fcnname, XSTR (operands[0], 0));
      operands[0] = get_symref (real_fcnname);
    }
  else
    {
      rtx data_access;

      emit_move_insn (gen_rtx (REG, SImode, 0),
		      force_reg (SImode, operands[0]));
      data_access = gen_rtx (MEM, SImode, operands[0]);
      RTX_UNCHANGING_P (data_access) = 1;
      operands[0] = copy_to_reg (data_access);
    }
}")

(define_insn ""
  [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
	 (match_operand 1 "" "g"))
   (clobber (reg:SI 15))]
  ""
  "balr%# r15,%0"
  [(set_attr "type" "call")
   (set_attr "length" "2")])

(define_insn ""
  [(call (mem:SI (match_operand:SI 0 "romp_symbolic_operand" "i"))
	 (match_operand 1 "" "g"))
   (clobber (reg:SI 15))]
  "GET_CODE (operands[0]) == SYMBOL_REF"
  "bali%# r15,%0"
  [(set_attr "type" "call")])

;; Call a function and return a value.
(define_expand "call_value"
  [(use (reg:SI 0))
   (parallel [(set (match_operand 0 "" "=fg")
		   (call (mem:SI (match_operand:SI 1 "address_operand" ""))
			 (match_operand 2 "" "")))
	      (clobber (reg:SI 15))])]
  ""
  "
{
  if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
    abort();

  operands[1] = XEXP (operands[1], 0);
  if (GET_CODE (operands[1]) == SYMBOL_REF)
    {
      extern rtx get_symref ();
      char *real_fcnname =
		(char *) alloca (strlen (XSTR (operands[1], 0)) + 2);

      /* Copy the data area address to r0.  */
      emit_move_insn (gen_rtx (REG, SImode, 0),
		      force_reg (SImode, operands[1]));
      strcpy (real_fcnname, \".\");
      strcat (real_fcnname, XSTR (operands[1], 0));
      operands[1] = get_symref (real_fcnname);
    }
  else
    {
      rtx data_access;

      emit_move_insn (gen_rtx (REG, SImode, 0),
		      force_reg (SImode, operands[1]));
      data_access = gen_rtx (MEM, SImode, operands[1]);
      RTX_UNCHANGING_P (data_access) = 1;
      operands[1] = copy_to_reg (data_access);
    }
}")

(define_insn ""
  [(set (match_operand 0 "" "=fg")
	(call (mem:SI (match_operand:SI 1 "register_operand" "b"))
	      (match_operand 2 "" "g")))
   (clobber (reg:SI 15))]
  ""
  "balr%# r15,%1"
  [(set_attr "length" "2")
   (set_attr "type" "call")])

(define_insn ""
  [(set (match_operand 0 "" "=fg")
	(call (mem:SI (match_operand:SI 1 "romp_symbolic_operand" "i"))
	      (match_operand 2 "" "g")))
   (clobber (reg:SI 15))]
  "GET_CODE (operands[1]) == SYMBOL_REF"
  "bali%# r15,%1"
  [(set_attr "type" "call")])

;; No operation insn.
(define_insn "nop"
  [(const_int 0)]
  ""
  "nopr r0"
  [(set_attr "type" "address")
   (set_attr "length" "2")
   (set_attr "cc" "none")])

;; Here are the floating-point operations.
;;
;; Start by providing DEFINE_EXPAND for each operation.
;; The insns will be handled with MATCH_OPERATOR; the methodology will be
;; discussed below.

;; First the conversion operations.

(define_expand "truncdfsf2"
  [(parallel [(set (match_operand:SF 0 "general_operand" "")
		   (float_truncate:SF (match_operand:DF 1 "general_operand" "")))
	      (clobber (reg:SI 0))
	      (clobber (reg:SI 15))])]
  ""
  "")

(define_expand "extendsfdf2"
  [(parallel [(set (match_operand:DF 0 "general_operand" "")
		   (float_extend:DF (match_operand:SF 1 "general_operand" "")))
	      (clobber (reg:SI 0))
	      (clobber (reg:SI 15))])]
  ""
  "")

(define_expand "floatsisf2"
  [(parallel [(set (match_operand:SF 0 "general_operand" "")
		   (float:SF (match_operand:SI 1 "general_operand" "")))
	      (clobber (reg:SI 0))
	      (clobber (reg:SI 15))])]
  ""
  "")

(define_expand "floatsidf2"
  [(parallel [(set (match_operand:DF 0 "general_operand" "")
		   (float:DF (match_operand:SI 1 "general_operand" "")))
	      (clobber (reg:SI 0))
	      (clobber (reg:SI 15))])]
  ""
  "")

(define_expand "fix_truncsfsi2"
  [(parallel [(set (match_operand:SI 0 "general_operand" "")
		   (fix:SI (match_operand:SF 1 "general_operand" "")))
	      (clobber (reg:SI 0))
	      (clobber (reg:SI 15))])]
  ""
  "")

(define_expand "fix_truncdfsi2"
  [(parallel [(set (match_operand:SI 0 "general_operand" "")
		   (fix:SI (match_operand:DF 1 "general_operand" "")))
	      (clobber (reg:SI 0))
	      (clobber (reg:SI 15))])]
  ""
  "")

;; Now the binary operations.

(define_expand "addsf3"
  [(parallel [(set (match_operand:SF 0 "general_operand" "")
		   (plus:SF (match_operand:SF 1 "general_operand" "")
			    (match_operand:SF 2 "general_operand" "")))
	      (clobber (reg:SI 0))
	      (clobber (reg:SI 15))])]
  ""
  "")

(define_expand "adddf3"
  [(parallel [(set (match_operand:DF 0 "general_operand" "")
		   (plus:DF (match_operand:DF 1 "general_operand" "")
			    (match_operand:DF 2 "general_operand" "")))
	       (clobber (reg:SI 0))
	       (clobber (reg:SI 15))])]
  ""
  "")

(define_expand "subsf3"
  [(parallel [(set (match_operand:SF 0 "general_operand" "")
		   (minus:SF (match_operand:SF 1 "general_operand" "")
			     (match_operand:SF 2 "general_operand" "")))
	      (clobber (reg:SI 0))
	      (clobber (reg:SI 15))])]
  ""
  "")

(define_expand "subdf3"
  [(parallel [(set (match_operand:DF 0 "general_operand" "")
		   (minus:DF (match_operand:DF 1 "general_operand" "")
			     (match_operand:DF 2 "general_operand" "")))
	      (clobber (reg:SI 0))
	      (clobber (reg:SI 15))])]
  ""
  "")

(define_expand "mulsf3"
  [(parallel [(set (match_operand:SF 0 "general_operand" "")
		   (mult:SF (match_operand:SF 1 "general_operand" "")
			    (match_operand:SF 2 "general_operand" "")))
	      (clobber (reg:SI 0))
	      (clobber (reg:SI 15))])]
  ""
  "")

(define_expand "muldf3"
  [(parallel [(set (match_operand:DF 0 "general_operand" "")
		   (mult:DF (match_operand:DF 1 "general_operand" "")
			    (match_operand:DF 2 "general_operand" "")))
	      (clobber (reg:SI 0))
	      (clobber (reg:SI 15))])]
  ""
  "")

(define_expand "divsf3"
  [(parallel [(set (match_operand:SF 0 "general_operand" "")
		   (div:SF (match_operand:SF 1 "general_operand" "")
			   (match_operand:SF 2 "general_operand" "")))
	      (clobber (reg:SI 0))
	      (clobber (reg:SI 15))])]
  ""
  "")

(define_expand "divdf3"
  [(parallel [(set (match_operand:DF 0 "general_operand" "")
		   (div:DF (match_operand:DF 1 "general_operand" "")
			   (match_operand:DF 2 "general_operand" "")))
	      (clobber (reg:SI 0))
	      (clobber (reg:SI 15))])]
  ""
  "")

;; Unary floating-point operations.
;;
;; Negations can be done without floating-point, since this is IEEE.
;; But we cannot do this if an operand is a hard FP register, since
;; the SUBREG we create would not be valid.
(define_expand "negsf2"
  [(set (match_operand:SF 0 "register_operand" "")
	(neg:SF (match_operand:SF 1 "register_operand" "")))]
  ""
  "
{
  if (! (GET_CODE (operands[0]) == REG
	 && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
	 && FP_REGNO_P (REGNO (operands[0])))
      && ! (GET_CODE (operands[1]) == REG
	    && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
	    && FP_REGNO_P (REGNO (operands[1]))))
    {
      rtx result;
      rtx target = operand_subword (operands[0], 0, 1, SFmode);

      result = expand_binop (SImode, xor_optab,
			     operand_subword_force (operands[1], 0, SFmode),
			     gen_rtx (CONST_INT, VOIDmode, 0x80000000),
			     target, 0, OPTAB_WIDEN);
      if (result == 0)
	abort ();

      if (result != target)
	emit_move_insn (result, target);

      /* Make a place for REG_EQUAL.  */
      emit_move_insn (operands[0], operands[0]);
      DONE;
    }
}")

(define_expand "negdf2"
  [(set (match_operand:DF 0 "register_operand" "")
	(neg:DF (match_operand:DF 1 "register_operand" "")))]
  ""
  "
{
  if (! (GET_CODE (operands[0]) == REG
	 && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
	 && FP_REGNO_P (REGNO (operands[0])))
      && ! (GET_CODE (operands[1]) == REG
	    && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
	    && FP_REGNO_P (REGNO (operands[1]))))
    {
      rtx result;
      rtx target = operand_subword (operands[0], 0, 1, DFmode);
      rtx insns;

      start_sequence ();
      result = expand_binop (SImode, xor_optab,
			     operand_subword_force (operands[1], 0, DFmode),
			     gen_rtx (CONST_INT, VOIDmode, 0x80000000),
			     target, 0, OPTAB_WIDEN);
      if (result == 0)
	abort ();

      if (result != target)
	emit_move_insn (result, target);
  
      emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
		      operand_subword_force (operands[1], 1, DFmode));

      insns = get_insns ();
      end_sequence ();

      emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
      DONE;
    }
}")

(define_expand "abssf2"
  [(parallel [(set (match_operand:SF 0 "general_operand" "")
		   (abs:SF (match_operand:SF 1 "general_operand" "")))
	      (clobber (reg:SI 0))
	      (clobber (reg:SI 15))])]
  ""
  "")

(define_expand "absdf2"
  [(parallel [(set (match_operand:DF 0 "general_operand" "")
		   (abs:DF (match_operand:DF 1 "general_operand" "")))
	      (clobber (reg:SI 0))
	      (clobber (reg:SI 15))])]
  ""
  "")

;; Any floating-point operation can be either SFmode or DFmode, and each
;; operand (including the output) can be either a normal operand or a
;; conversion from a normal operand.
;;
;; We use MATCH_OPERATOR to match a floating-point binary or unary operator
;; and input and output conversions.  So we need 2^N patterns for each type
;; of operation, where N is the number of operands, including the output.
;; There are thus a total of 14 patterns, 8 for binary operations, 4 for
;; unary operations and two for conversion/move operations (only one
;; operand can have a conversion for move operations).  In addition, we have
;; to be careful that a floating-point reload register doesn't get allocated
;; for an integer.  We take care of this for inputs with PREFERRED_RELOAD_CLASS
;; but need to have two different constraints for outputs.  This means that
;; we have to duplicate each pattern where the output could be an integer.
;; This adds another 7 patterns, for a total of 21.

;; Start with conversion operations (moves are done above).

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g")
	(match_operator 1 "float_conversion"
		[(match_operand 2 "general_operand" "frg")]))
   (clobber (match_operand:SI 3 "reg_0_operand" "=&z"))
   (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))]
  ""
  "*
{ return output_fpop (SET, operands[0], operands[2], 0, insn);
}"
  [(set_attr "type" "fp")])

(define_insn ""
  [(set (match_operand 0 "general_operand" "=frg")
	(match_operator 1 "float_conversion"
		[(match_operand 2 "general_operand" "frg")]))
   (clobber (match_operand:SI 3 "reg_0_operand" "=&z"))
   (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))]
  ""
  "*
{ return output_fpop (SET, operands[0], operands[2], 0, insn);
}"
  [(set_attr "type" "fp")])

;; Next, binary floating-point operations.

(define_insn ""
  [(set (match_operand 0 "general_operand" "=frg")
	(match_operator 1 "float_binary"
		[(match_operand 2 "general_operand" "frg")
		 (match_operand 3 "general_operand" "frg")]))
   (clobber (match_operand:SI 4 "reg_0_operand" "=&z"))
   (clobber (match_operand:SI 5 "reg_15_operand" "=&t"))]
  "check_precision (GET_MODE (operands[1]), operands[2], operands[3])"
  "*
{ return output_fpop (GET_CODE (operands[1]), operands[0], 
		      operands[2], operands[3], insn);
}"
  [(set_attr "type" "fp")])

(define_insn ""
  [(set (match_operand 0 "general_operand" "=frg")
	(match_operator 1 "float_binary"
		[(match_operand 2 "general_operand" "frg")
		 (match_operator 3 "float_conversion"
			[(match_operand 4 "general_operand" "frg")])]))
   (clobber (match_operand:SI 5 "reg_0_operand" "=&z"))
   (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))]
  "check_precision (GET_MODE (operands[1]), operands[2], operands[4])"
  "*
{ return output_fpop (GET_CODE (operands[1]), operands[0], 
		      operands[2], operands[4], insn);
}"
  [(set_attr "type" "fp")])

(define_insn ""
  [(set (match_operand 0 "general_operand" "=frg")
	(match_operator 1 "float_binary"
		[(match_operator 2 "float_conversion"
			[(match_operand 3 "general_operand" "frg")])
		 (match_operand 4