we32k.md

早期freebsd实现

(define_insn "truncsihi2"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
        (truncate:HI (match_operand:SI 1 "general_operand" "mri")))]
  ""
  "movtwh %1, %0")

(define_insn "truncsiqi2"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
        (truncate:QI (match_operand:SI 1 "general_operand" "mri")))]
  ""
  "movtwb %1, %0")

(define_insn "trunchiqi2"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
        (truncate:QI (match_operand:HI 1 "general_operand" "mri")))]
  ""
  "movthb %1, %0")

;; sign-extend move instructions

(define_insn "extendsfdf2"
  [(clobber (reg:SI 0))
   (clobber (reg:SI 1))
   (clobber (reg:SI 2))
   (set (match_operand:DF 0 "nonimmediate_operand" "=or")
        (float_extend:DF (match_operand:SF 1 "general_operand" "mrF")))]
  ""
  "*
  {
  rtx xoperands[2];

  output_asm_insn(\"pushw %1\", operands);
  output_asm_insn(\"call &1, _fstod\");

  if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 0) {
    xoperands[0] = operands[0];
    xoperands[1] = gen_rtx(REG, DFmode, 0);
    output_move_double(xoperands);
    }

  return \"\";
  }")

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
        (sign_extend:SI (match_operand:HI 1 "general_operand" "mri")))]
  ""
  "movbhw %1, %0")

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
        (sign_extend:SI (match_operand:QI 1 "general_operand" "mri")))]
  ""
  "movbbw %1, %0")

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
        (sign_extend:HI (match_operand:QI 1 "general_operand" "mri")))]
  ""
  "movbbh %1, %0")

;; zero-extend move instructions

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
        (zero_extend:SI (match_operand:HI 1 "general_operand" "mri")))]
  ""
  "movzhw %1, %0")

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
        (zero_extend:SI (match_operand:QI 1 "general_operand" "mri")))]
  ""
  "movzbw %1, %0")

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
        (zero_extend:HI (match_operand:QI 1 "general_operand" "mri")))]
  ""
  "movzbh %1, %0")

;; bit field instructions

(define_insn "extzv"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
        (zero_extract:SI (match_operand:SI 1 "general_operand" "mri")
                         (match_operand:SI 2 "immediate_operand" "i")
                         (match_operand:SI 3 "general_operand" "mri")))]
  ""
  "*
  {

  operands[2] = gen_rtx(CONST_INT, SImode, INTVAL(operands[2]) - 1);
  output_asm_insn(\"EXTFW %2, %3, %1, %0\",operands);

  return \"\";
  }")

(define_insn ""
  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
        (zero_extract:SI (match_operand:HI 1 "general_operand" "mri")
                         (match_operand:SI 2 "immediate_operand" "i")
                         (match_operand:SI 3 "general_operand" "mri")))]
  ""
  "*
  {

  operands[2] = gen_rtx(CONST_INT, SImode, INTVAL(operands[2]) - 1);
  output_asm_insn(\"EXTFH %2, %3, {uhalf}%1, {uword}%0\",operands);

  return \"\";
  }")

(define_insn ""
  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
        (zero_extract:SI (match_operand:QI 1 "general_operand" "mri")
                         (match_operand:SI 2 "immediate_operand" "i")
                         (match_operand:SI 3 "general_operand" "mri")))]
  ""
  "*
  {

  operands[2] = gen_rtx(CONST_INT, SImode, INTVAL(operands[2]) - 1);
  output_asm_insn(\"EXTFB %2, %3, {ubyte}%1, {uword}%0\",operands);

  return \"\";
  }")

(define_insn "insv"
  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+mr")
                         (match_operand:SI 1 "immediate_operand" "i")
                         (match_operand:SI 2 "general_operand" "mri"))
        (match_operand:SI 3 "general_operand" "mri"))]
  ""
  "*
  {

  operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) - 1);
  output_asm_insn(\"INSFW %1, %2, %3, %0\",operands);

  return \"\";
  }")

(define_insn ""
  [(set (zero_extract:SI (match_operand:HI 0 "nonimmediate_operand" "+mr")
                         (match_operand:SI 1 "immediate_operand" "i")
                         (match_operand:SI 2 "general_operand" "mri"))
        (match_operand:SI 3 "general_operand" "mri"))]
  ""
  "*
  {

  operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) - 1);
  output_asm_insn(\"INSFH %1, %2, {uword}%3, {uhalf}%0\",operands);

  return \"\";
  }")

(define_insn ""
  [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+mr")
                         (match_operand:SI 1 "immediate_operand" "i")
                         (match_operand:SI 2 "general_operand" "mri"))
        (match_operand:SI 3 "general_operand" "mri"))]
  ""
  "*
  {

  operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) - 1);
  output_asm_insn(\"INSFB %1, %2, {uword}%3, {ubyte}%0\",operands);

  return \"\";
  }")

;; conditional branch instructions

(define_insn "beq"
  [(set (pc) (if_then_else (eq (cc0) (const_int 0))
                           (label_ref (match_operand 0 "" ""))
                           (pc)))]
  ""
  "je %l0")

(define_insn "bne"
  [(set (pc) (if_then_else (ne (cc0) (const_int 0))
                           (label_ref (match_operand 0 "" ""))
                           (pc)))]
  ""
  "jne %l0")

(define_insn "bgt"
  [(set (pc) (if_then_else (gt (cc0) (const_int 0))
                           (label_ref (match_operand 0 "" ""))
                           (pc)))]
  ""
  "jg %l0")

(define_insn "bgtu"
  [(set (pc) (if_then_else (gtu (cc0) (const_int 0))
                           (label_ref (match_operand 0 "" ""))
                           (pc)))]
  ""
  "jgu %l0")

(define_insn "blt"
  [(set (pc) (if_then_else (lt (cc0) (const_int 0))
                           (label_ref (match_operand 0 "" ""))
                           (pc)))]
  ""
  "jl %l0")

(define_insn "bltu"
  [(set (pc) (if_then_else (ltu (cc0) (const_int 0))
                           (label_ref (match_operand 0 "" ""))
                           (pc)))]
  ""
  "jlu %l0")

(define_insn "bge"
  [(set (pc) (if_then_else (ge (cc0) (const_int 0))
                           (label_ref (match_operand 0 "" ""))
                           (pc)))]
  ""
  "jge %l0")

(define_insn "bgeu"
  [(set (pc) (if_then_else (geu (cc0) (const_int 0))
                           (label_ref (match_operand 0 "" ""))
                           (pc)))]
  ""
  "jgeu %l0")

(define_insn "ble"
  [(set (pc) (if_then_else (le (cc0) (const_int 0))
                           (label_ref (match_operand 0 "" ""))
                           (pc)))]
  ""
  "jle %l0")

(define_insn "bleu"
  [(set (pc) (if_then_else (leu (cc0) (const_int 0))
                           (label_ref (match_operand 0 "" ""))
                           (pc)))]
  ""
  "jleu %l0")

;; reverse-conditional branch instructions

(define_insn ""
  [(set (pc) (if_then_else (eq (cc0) (const_int 0))
                           (pc)
                           (label_ref (match_operand 0 "" ""))))]
  ""
  "jne %l0")

(define_insn ""
  [(set (pc) (if_then_else (ne (cc0) (const_int 0))
                           (pc)
                           (label_ref (match_operand 0 "" ""))))]
  ""
  "je %l0")

(define_insn ""
  [(set (pc) (if_then_else (gt (cc0) (const_int 0))
                           (pc)
                           (label_ref (match_operand 0 "" ""))))]
  ""
  "jle %l0")

(define_insn ""
  [(set (pc) (if_then_else (gtu (cc0) (const_int 0))
                           (pc)
                           (label_ref (match_operand 0 "" ""))))]
  ""
  "jleu %l0")

(define_insn ""
  [(set (pc) (if_then_else (lt (cc0) (const_int 0))
                           (pc)
                           (label_ref (match_operand 0 "" ""))))]
  ""
  "jge %l0")

(define_insn ""
  [(set (pc) (if_then_else (ltu (cc0) (const_int 0))
                           (pc)
                           (label_ref (match_operand 0 "" ""))))]
  ""
  "jgeu %l0")

(define_insn ""
  [(set (pc) (if_then_else (ge (cc0) (const_int 0))
                           (pc)
                           (label_ref (match_operand 0 "" ""))))]
  ""
  "jl %l0")

(define_insn ""
  [(set (pc) (if_then_else (geu (cc0) (const_int 0))
                           (pc)
                           (label_ref (match_operand 0 "" ""))))]
  ""
  "jlu %l0")

(define_insn ""
  [(set (pc) (if_then_else (le (cc0) (const_int 0))
                           (pc)
                           (label_ref (match_operand 0 "" ""))))]
  ""
  "jg %l0")

(define_insn ""
  [(set (pc) (if_then_else (leu (cc0) (const_int 0))
                           (pc)
                           (label_ref (match_operand 0 "" ""))))]
  ""
  "jgu %l0")

;; call instructions

(define_insn "call"
  [(call (match_operand:QI 0 "memory_operand" "m")
         (match_operand:SI 1 "immediate_operand" "i"))]
  ""
  "call %1/4, %0")

(define_insn "call_value"
  [(set (match_operand 0 "register_operand" "=r")
        (call (match_operand:QI 1 "memory_operand" "m")
              (match_operand:SI 2 "immediate_operand" "i")))]
  ""
  "call %2/4, %1")

;; No-op instruction

(define_insn "nop"
  [(const_int 0)]
  ""
  "NOP")

;; jump through a dispatch table instruction

(define_expand "casesi"
  [(use (match_operand:SI 0 "general_operand" "mri"))
   (set (cc0) (compare (match_dup 5)
                       (match_operand:SI 1 "general_operand" "mri")))
   (set (pc) (if_then_else (lt (cc0) (const_int 0))
                           (label_ref (match_operand 4 "" ""))
                           (pc)))
   (set (match_dup 5) (minus:SI (match_dup 5)
                                (match_dup 1)))
   (set (cc0) (compare (match_dup 5)
                       (match_operand:SI 2 "general_operand" "mri")))
   (set (pc) (if_then_else (gtu (cc0) (const_int 0))
                           (label_ref (match_dup 4))
                           (pc)))
   (set (match_dup 5) (ashift:SI (match_dup 5)
                                 (const_int 2)))
   (set (pc) (mem:SI (plus:SI (label_ref (match_operand 3 "" ""))
                              (match_dup 5))))]
  ""
  "
  {
  operands[5] = gen_reg_rtx(GET_MODE (operands[0]));
  emit_move_insn(operands[5], operands[0]);
  }")

;; jump instructions

(define_insn ""
  [(set (pc) (mem:SI (match_operand:SI 0 "address_operand" "p")))]
  "GET_CODE (operands[0]) != MEM"
  "jmp *%a0")

(define_insn "indirect_jump"
  [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
  ""
  "jmp %a0")

(define_insn "jump"
  [(set (pc) (label_ref (match_operand 0 "" "")))]
  ""
  "jmp %l0")

;; peephole optimizations

(define_peephole
  [(set (match_operand:SI 0 "register_operand" "=r")
        (match_operand:SI 1 "nonimmediate_operand" "or"))
   (set (match_operand:SI 2 "register_operand" "=r")
        (mem:SI (match_dup 0)))]
  "REGNO (operands[0]) == REGNO (operands[2]) && (REG_P (operands[1]) || offsettable_memref_p (operands[1]))"
  "movw %a1, %0")

(define_peephole
  [(set (match_operand:SI 0 "register_operand" "=r")
        (match_operand:SI 1 "nonimmediate_operand" "or"))
   (set (match_operand:HI 2 "register_operand" "=r")
        (mem:HI (match_dup 0)))]
  "REGNO (operands[0]) == REGNO (operands[2]) && (REG_P (operands[1]) || offsettable_memref_p (operands[1]))"
  "movh %a1, %0")

(define_peephole
  [(set (match_operand:SI 0 "register_operand" "=r")
        (match_operand:SI 1 "nonimmediate_operand" "or"))
   (set (match_operand:QI 2 "register_operand" "=r")
        (mem:QI (match_dup 0)))]
  "REGNO (operands[0]) == REGNO (operands[2]) && (REG_P (operands[1]) || offsettable_memref_p (operands[1]))"
  "movb %a1, %0")