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(define_insn "lshlsi3" [(set (match_operand:SI 0 "register_operand" "=d,a") (lshift:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "nonmemory_operand" "di,ai")))] "" "*{ if (operands[2] == const1_rtx) return \"add.w %0,%0\"; else if (TARGET_C2 && S_REG_P (operands[0])) return \"shf.w %2,%0\"; else return \"shf %2,%0\";}")(define_insn "ashlsi3" [(set (match_operand:SI 0 "register_operand" "=d,a") (ashift:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "nonmemory_operand" "di,ai")))] "" "*{ if (operands[2] == const1_rtx) return \"add.w %0,%0\"; else if (TARGET_C2 && S_REG_P (operands[0])) return \"shf.w %2,%0\"; else return \"shf %2,%0\";}")(define_expand "lshrsi3" [(set (match_operand:SI 0 "register_operand" "") (lshiftrt:SI (match_operand:SI 1 "register_operand" "") (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))] "" "operands[2] = negate_rtx (SImode, operands[2]);")(define_insn "" [(set (match_operand:SI 0 "register_operand" "=d,a") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0") (neg:SI (match_operand:SI 2 "nonmemory_operand" "di,ai"))))] "" "*{ if (A_REG_P (operands[0])) return \"shf %2,%0\"; else if (TARGET_C2) return \"shf.w %2,%0\"; else return \"ld.u #0,%0\;shf %2,%0\";}")(define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "" "*{ if (A_REG_P (operands[0])) return \"shf #%n2,%0\"; else if (TARGET_C2) return \"shf.w #%n2,%0\"; else return \"ld.u #0,%0\;shf #%n2,%0\";}")(define_expand "ashrsi3" [(set (match_operand:SI 0 "register_operand" "=d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))] "" "operands[2] = negate_rtx (SImode, operands[2]);")(define_insn "" [(set (match_operand:SI 0 "register_operand" "=&d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))] "" "cvtw.l %1,%0\;shf %2,%0")(define_insn "" [(set (match_operand:SI 0 "register_operand" "=&d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "immediate_operand" "i")))] "" "cvtw.l %1,%0\;shf #%n2,%0")(define_insn "lshldi3" [(set (match_operand:DI 0 "register_operand" "=d") (lshift:DI (match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "nonmemory_operand" "di")))] "" "shf %2,%0")(define_insn "ashldi3" [(set (match_operand:DI 0 "register_operand" "=d") (ashift:DI (match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "nonmemory_operand" "di")))] "" "shf %2,%0")(define_expand "lshrdi3" [(set (match_operand:DI 0 "register_operand" "=d") (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))] "" "operands[2] = negate_rtx (SImode, operands[2]);")(define_insn "" [(set (match_operand:DI 0 "register_operand" "=d") (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))] "" "shf %2,%0")(define_insn "" [(set (match_operand:DI 0 "register_operand" "=d") (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "" "shf #%n2,%0");; signed a >> b is;; ((a >> b) ^ signbit) - signbit;; where signbit is (1 << 63) >> b(define_expand "ashrdi3" [(match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "register_operand" "") (match_operand:SI 2 "nonmemory_operand" "") (match_dup 3)] "" "{ if (GET_CODE (operands[2]) == CONST_INT) { int rshift = INTVAL (operands[2]); if (rshift < 0) operands[3] = force_reg (DImode, immed_double_const (0, 0, DImode)); else if (rshift < 32) operands[3] = force_reg (DImode, immed_double_const (0, 1 << (31 - rshift), DImode)); else if (rshift < 64) operands[3] = force_reg (DImode, immed_double_const (1 << (63 - rshift), 0, DImode)); else operands[3] = force_reg (DImode, immed_double_const (0, 0, DImode)); } else { operands[3] = force_reg (DImode, immed_double_const (0, 1 << 31, DImode)); emit_insn (gen_lshrdi3 (operands[3], operands[3], operands[2])); } emit_insn (gen_lshrdi3 (operands[0], operands[1], operands[2])); emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (XOR, DImode, operands[0], operands[3]))); emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (MINUS, DImode, operands[0], operands[3]))); DONE;}");; __builtin instructions(define_insn "sqrtdf2" [(set (match_operand:DF 0 "register_operand" "=d") (sqrt:DF (match_operand:DF 1 "register_operand" "0")))] "TARGET_C2" "sqrt.d %0")(define_insn "sqrtsf2" [(set (match_operand:SF 0 "register_operand" "=d") (sqrt:SF (match_operand:SF 1 "register_operand" "0")))] "TARGET_C2" "sqrt.s %0");(define_insn ""; [(set (match_operand:SI 0 "register_operand" "=d"); (minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d")); (const_int 1)))]; ""; "tzc %1,%0\;le.w #32,%0\;jbrs.f .+6\;ld.w #-1,%0");;(define_expand "ffssi2"; [(set (match_operand:SI 0 "register_operand" "=d"); (minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d")); (const_int 1))); (set (match_dup 0); (plus:SI (match_dup 0); (const_int 1)))]; ""; "")(define_insn "abssf2" [(set (match_operand:SF 0 "register_operand" "=d") (abs:SF (match_operand:SF 1 "register_operand" "0")))] "" "and #0x7fffffff,%0")(define_expand "absdf2" [(set (subreg:DI (match_operand:DF 0 "register_operand" "=d") 0) (and:DI (subreg:DI (match_operand:DF 1 "register_operand" "d") 0) (match_dup 2)))] "" "operands[2] = force_reg (DImode, immed_double_const (-1, 0x7fffffff, DImode));");; Jumps(define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "jbr %l0")(define_insn "beq" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return gen_cmp (operands[0], \"eq\", 't'); ")(define_insn "bne" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return gen_cmp (operands[0], \"eq\", 'f'); ")(define_insn "bgt" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return gen_cmp (operands[0], \"le\", 'f'); ")(define_insn "bgtu" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return gen_cmp (operands[0], \"leu\", 'f'); ")(define_insn "blt" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return gen_cmp (operands[0], \"lt\", 't'); ")(define_insn "bltu" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return gen_cmp (operands[0], \"ltu\", 't'); ")(define_insn "bge" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return gen_cmp (operands[0], \"lt\", 'f'); ")(define_insn "bgeu" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return gen_cmp (operands[0], \"ltu\", 'f'); ")(define_insn "ble" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return gen_cmp (operands[0], \"le\", 't'); ")(define_insn "bleu" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return gen_cmp (operands[0], \"leu\", 't'); ")(define_insn "" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return gen_cmp (operands[0], \"eq\", 'f'); ")(define_insn "" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return gen_cmp (operands[0], \"eq\", 't'); ")(define_insn "" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return gen_cmp (operands[0], \"le\", 't'); ")(define_insn "" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return gen_cmp (operands[0], \"leu\", 't'); ")(define_insn "" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return gen_cmp (operands[0], \"lt\", 'f'); ")(define_insn "" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return gen_cmp (operands[0], \"ltu\", 'f'); ")(define_insn "" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return gen_cmp (operands[0], \"lt\", 't'); ")(define_insn "" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return gen_cmp (operands[0], \"ltu\", 't'); ")(define_insn "" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return gen_cmp (operands[0], \"le\", 'f'); ")(define_insn "" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return gen_cmp (operands[0], \"leu\", 'f'); ");; - Calls;;;; arg count word may be omitted to save a push and let gcc try to;; combine the arg list pop. RETURN_POPS_ARGS from tm.h decides this.(define_insn "call" [(call (match_operand:QI 0 "memory_operand" "m") (match_operand 1 "" "g"))] "" "* return output_call (insn, operands[0], operands[1]);")(define_insn "call_value" [(set (match_operand 0 "" "=g") (call (match_operand:QI 1 "memory_operand" "m") (match_operand 2 "" "g")))] "" "* return output_call (insn, operands[1], operands[2]);")(define_insn "return" [(return)] "" "rtn")(define_insn "nop" [(const_int 0)] "" "nop")(define_insn "tablejump" [(set (pc) (match_operand:SI 0 "address_operand" "p")) (use (label_ref (match_operand 1 "" "")))] "" "jmp %a0")(define_insn "indirect_jump" [(set (pc) (match_operand:SI 0 "address_operand" "p"))] "" "jmp %a0");;- Local variables:;;- mode:emacs-lisp;;- comment-start: ";;- ";;- eval: (set-syntax-table (copy-sequence (syntax-table)));;- eval: (modify-syntax-entry ?[ "(]");;- eval: (modify-syntax-entry ?] ")[");;- eval: (modify-syntax-entry ?{ "(}");;- eval: (modify-syntax-entry ?} "){");;- End:
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