convex.md

早期freebsd实现

;;- Machine description for GNU compiler
;;- Convex Version
;;   Copyright (C) 1991 Free Software Foundation, Inc.

;; This file is part of GNU CC.

;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.

;; GNU CC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.

;; Scheduling defs
;;
;; Insn scheduling is not used at present.  Scheduling increases
;; register pressure so much that many spills are generated
;; even for very small functions.

;; Compares

(define_insn "tstsi"
  [(set (cc0)
	(match_operand:SI 0 "register_operand" "r"))]
  ""
  "* return set_cmp (operands[0], const0_rtx, 'w');")

(define_insn "tsthi"
  [(set (cc0)
	(match_operand:HI 0 "register_operand" "r"))]
  ""
  "* return set_cmp (operands[0], const0_rtx, 'h');")

(define_expand "tstqi"
  [(set (match_dup 1)
	(sign_extend:SI (match_operand:QI 0 "register_operand" "r")))
   (set (cc0)
	(match_dup 1))]
  ""
  "operands[1] = gen_reg_rtx (SImode);")

(define_expand "tstdi"
  [(parallel [(set (cc0) (match_operand:DI 0 "register_operand" "d"))
	      (use (match_dup 1))])]
  ""
  "operands[1] = force_reg (DImode, const0_rtx);")

(define_insn ""
  [(set (cc0) (match_operand:DI 0 "register_operand" "d"))
   (use (match_operand:DI 1 "register_operand" "d"))]
  ""
  "* return set_cmp (operands[0], operands[1], 'l');")

(define_expand "tstdf"
  [(set (cc0)
	(compare (match_operand:DF 0 "register_operand" "d")
		 (match_dup 1)))]
  ""
  "operands[1] = force_reg (DFmode, CONST0_RTX (DFmode));")

(define_insn "tstsf"
  [(set (cc0)
	(match_operand:SF 0 "register_operand" "d"))]
  ""
  "* return set_cmp (operands[0], CONST0_RTX (SFmode), 's');")

(define_insn "cmpsi"
  [(set (cc0)
	(compare (match_operand:SI 0 "register_operand" "d,a,i,r")
		 (match_operand:SI 1 "nonmemory_operand" "d,a,r,i")))]
  ""
  "* return set_cmp (operands[0], operands[1], 'w');")

(define_insn "cmphi"
  [(set (cc0)
	(compare (match_operand:HI 0 "register_operand" "d,a,r,i")
		 (match_operand:HI 1 "nonmemory_operand" "d,a,i,r")))]
  ""
  "* return set_cmp (operands[0], operands[1], 'h');")

(define_insn "cmpqi"
  [(set (cc0)
	(compare (match_operand:QI 0 "register_operand" "d")
		 (match_operand:QI 1 "register_operand" "d")))]
  ""
  "* return set_cmp (operands[0], operands[1], 'b');")

(define_insn "cmpdi"
  [(set (cc0)
	(compare (match_operand:DI 0 "register_operand" "d")
		 (match_operand:DI 1 "register_operand" "d")))]
  ""
  "* return set_cmp (operands[0], operands[1], 'l');")

(define_insn "cmpdf"
  [(set (cc0)
	(compare (match_operand:DF 0 "register_operand" "d")
		 (match_operand:DF 1 "register_operand" "d")))]
  ""
  "* return set_cmp (operands[0], operands[1], 'd');")

(define_insn "cmpsf"
  [(set (cc0)
	(compare (match_operand:SF 0 "nonmemory_operand" "dF,d")
		 (match_operand:SF 1 "nonmemory_operand" "d,F")))]
  ""
  "* return set_cmp (operands[0], operands[1], 's');")

;; Moves

;(define_insn "movtf"
;  [(set (match_operand:TF 0 "general_operand" "=g,d")
;	(match_operand:TF 1 "general_operand" "d,g"))]
;  ""
;  "*
;{
;  rtx opaddr = 0;
;  rtx xoperands[4];
;  xoperands[0] = operands[0];
;  xoperands[2] = operands[1];
;
;  if (REG_P (operands[0]))
;    xoperands[1] = gen_rtx (REG, TFmode, REGNO (operands[0]) + 1);
;  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
;    xoperands[1] = 0;
;  else if (offsettable_memref_p (operands[0]))
;    xoperands[1] = adj_offsettable_operand (operands[0], 8);
;  else
;    {
;      opaddr = XEXP (operands[0], 0);
;      xoperands[0] = gen_rtx (MEM, TFmode, gen_rtx (REG, SImode, 13));
;      xoperands[1] = adj_offsettable_operand (xoperands[0], 8);
;    }
;
;  if (REG_P (operands[1]))
;    xoperands[3] = gen_rtx (REG, TFmode, REGNO (operands[1]) + 1);
;  else if (offsettable_memref_p (operands[1]))
;    xoperands[3] = adj_offsettable_operand (operands[1], 8);
;  else
;    {
;      opaddr = XEXP (operands[1], 0);
;      xoperands[2] = gen_rtx (MEM, TFmode, gen_rtx (REG, SImode, 13));
;      xoperands[3] = adj_offsettable_operand (xoperands[2], 8);
;    }
;
;  if (opaddr)
;    output_asm_insn (\"psh.w a5\;ld.w %0,a5\", &opaddr);
;  if (push_operand (operands[0], TFmode))
;    output_asm_insn (\"psh.l %3\;psh.l %2\", xoperands);
;  else if (GET_CODE (operands[0]) == MEM)
;    output_asm_insn (\"st.l %2,%0\;st.l %3,%1\", xoperands);
;  else if (GET_CODE (operands[1]) == REG)
;    output_asm_insn (\"mov %2,%0\;mov %3,%1\", xoperands);
;  else
;    output_asm_insn (\"ld.l %2,%0\;ld.l %3,%1\", xoperands);
;  if (opaddr)
;    output_asm_insn (\"pop.w a5\");
;  return \"\";
;}")

(define_insn "movdf"
  [(set (match_operand:DF 0 "general_operand" "=g,d")
	(match_operand:DF 1 "general_operand" "d,dmG"))]
  ""
  "*
{
  if (push_operand (operands[0], DFmode))
    return \"psh.l %1\";
  else if (GET_CODE (operands[0]) == MEM)
    return \"st.l %1,%0\";
  else if (GET_CODE (operands[1]) == REG)
    return \"mov %1,%0\";
  else if (GET_CODE (operands[1]) == CONST_DOUBLE && LD_D_P (operands[1]))
    {
      operands[1] = gen_rtx (CONST_INT, VOIDmode,
			     const_double_high_int (operands[1]));
      return \"ld.d %1,%0\";
    }
  else if (GET_CODE (operands[1]) == CONST_DOUBLE && LD_L_P (operands[1]))
    {
      operands[1] = gen_rtx (CONST_INT, VOIDmode,
			     const_double_low_int (operands[1]));
      return \"ld.l %1,%0\";
    }
  else
    return \"ld.l %1,%0\";
}")

(define_insn "movsf"
  [(set (match_operand:SF 0 "general_operand" "=g,d")
	(match_operand:SF 1 "general_operand" "d,gF"))]
  ""
  "*
{
  if (push_operand (operands[0], SFmode))
    return \"psh.w %1\";
  else if (GET_CODE (operands[0]) == MEM)
    return \"st.s %1,%0\";
  else if (GET_CODE (operands[1]) == REG)
    return \"mov.s %1,%0\";
  else
    return \"ld.s %1,%0\";
}")

(define_insn "movdi"
  [(set (match_operand:DI 0 "general_operand" "=g,d")
	(match_operand:DI 1 "general_operand" "d,dmiG"))]
  ""
  "*
{
  if (push_operand (operands[0], DImode))
    return \"psh.l %1\";
  else if (GET_CODE (operands[0]) == MEM)
    return \"st.l %1,%0\";
  else if (GET_CODE (operands[1]) == REG)
    return \"mov %1,%0\";
  else if (GET_CODE (operands[1]) == CONST_DOUBLE && LD_D_P (operands[1]))
    {
      operands[1] = gen_rtx (CONST_INT, VOIDmode,
			     const_double_high_int (operands[1]));
      return \"ld.d %1,%0\";
    }
  else
    return \"ld.l %1,%0\";
}")

;; Special case of movsi, needed to express A-reg preference.

(define_insn ""
  [(set (match_operand:SI 0 "push_operand" "=<")
	(plus:SI (match_operand:SI 1 "register_operand" "a")
		 (match_operand:SI 2 "immediate_operand" "i")))]
  "operands[1] != stack_pointer_rtx"
  "pshea %a2(%1)")

;; General movsi.  Constraints will be selected based on TARGET_INDIRECTS
;; to avoid indirect addressing on C3, where it is slow.

(define_expand "movsi"
  [(set (match_operand:SI 0 "general_operand" "")
	(match_operand:SI 1 "general_operand" ""))]
  ""
  "")

(define_insn ""
  [(set (match_operand:SI 0 "push_operand" "=<,<")
	(match_operand:SI 1 "general_operand" "Ad,io"))]
  ""
  "@
   psh.w %1
   pshea %a1")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g,r,<")
	(match_operand:SI 1 "general_operand" "r,g,io"))]
  "TARGET_INDIRECTS"
  "*
{ 
  if (push_operand (operands[0], SImode))
    {
      if (GET_CODE (operands[1]) == REG)
	return \"psh.w %1\";
      else
        return \"pshea %a1\";
    }
  if (GET_CODE (operands[0]) == MEM)
    return \"st.w %1,%0\";
  if (GET_CODE (operands[1]) != REG)
    return \"ld.w %1,%0\";
  if (S_REG_P (operands[0]) && S_REG_P (operands[1]))
    return \"mov.w %1,%0\";
  return \"mov %1,%0\";
}")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g,r,<")
	(match_operand:SI 1 "general_operand" "r,g,i"))]
  "! TARGET_INDIRECTS"
  "*
{ 
  if (push_operand (operands[0], SImode))
    {
      if (GET_CODE (operands[1]) == REG)
	return \"psh.w %1\";
      else
        return \"pshea %a1\";
    }
  if (GET_CODE (operands[0]) == MEM)
    return \"st.w %1,%0\";
  if (GET_CODE (operands[1]) != REG)
    return \"ld.w %1,%0\";
  if (S_REG_P (operands[0]) && S_REG_P (operands[1]))
    return \"mov.w %1,%0\";
  return \"mov %1,%0\";
}")

(define_insn "movstrictsi"
  [(set (strict_low_part (match_operand:SI 0 "general_operand" "+g,r"))
	(match_operand:SI 1 "general_operand" "r,g"))]
  ""
  "*
{ 
  if (GET_CODE (operands[0]) == MEM)
    return \"st.w %1,%0\";
  if (GET_CODE (operands[1]) != REG)
    return \"ld.w %1,%0\";
  if (S_REG_P (operands[0]) && S_REG_P (operands[1]))
    return \"mov.w %1,%0\";
  return \"mov %1,%0\";
}")

(define_insn "movhi"
  [(set (match_operand:HI 0 "general_operand" "=g,r")
	(match_operand:HI 1 "general_operand" "r,g"))]
  ""
  "*
{
  if (push_operand (operands[0], HImode))
    abort ();
  else if (GET_CODE (operands[0]) == MEM)
    return \"st.h %1,%0\";
  else if (GET_CODE (operands[1]) == REG) 
    {
      if (S_REG_P (operands[0]) && S_REG_P (operands[1]))
	return \"mov.w %1,%0\";
      else
        return \"mov %1,%0\";
    }
  else if (GET_CODE (operands[1]) == CONST_INT)
    return \"ld.w %1,%0\";
  else
    return \"ld.h %1,%0\";
}")

(define_insn "movqi"
  [(set (match_operand:QI 0 "general_operand" "=g,r")
	(match_operand:QI 1 "general_operand" "r,g"))]
  ""
  "*
{
  if (push_operand (operands[0], QImode))
    abort ();
  else if (GET_CODE (operands[0]) == MEM)
    return \"st.b %1,%0\";
  else if (GET_CODE (operands[1]) == REG)
    {
      if (S_REG_P (operands[0]) && S_REG_P (operands[1]))
	return \"mov.w %1,%0\";
      else
        return \"mov %1,%0\";
    }
  else if (GET_CODE (operands[1]) == CONST_INT)
    return \"ld.w %1,%0\";
  else
    return \"ld.b %1,%0\";
}")

;; Extension and truncation insns.
;; Those for integer source operand
;; are ordered widest source type first.

(define_insn "truncsiqi2"
  [(set (match_operand:QI 0 "register_operand" "=d,a")
	(truncate:QI (match_operand:SI 1 "register_operand" "d,a")))]
  ""
  "cvtw.b %1,%0")

(define_insn "truncsihi2"
  [(set (match_operand:HI 0 "register_operand" "=d,a")
	(truncate:HI (match_operand:SI 1 "register_operand" "d,a")))]
  ""
  "cvtw.h %1,%0")

(define_insn "trunchiqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(truncate:QI (match_operand:HI 1 "register_operand" "0")))]
  ""
  "")

(define_insn "truncdisi2"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(truncate:SI (match_operand:DI 1 "register_operand" "d")))]
  ""
  "cvtl.w %1,%0")

(define_insn "extendsidi2"
  [(set (match_operand:DI 0 "register_operand" "=d")
	(sign_extend:DI (match_operand:SI 1 "register_operand" "d")))]
  ""
  "cvtw.l %1,%0")

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "=d,a")
	(sign_extend:SI (match_operand:HI 1 "register_operand" "d,a")))]
  ""
  "cvth.w %1,%0")

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=d,a")
	(sign_extend:HI (match_operand:QI 1 "register_operand" "d,a")))]
  ""
  "cvtb.w %1,%0")

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "=d,a")
	(sign_extend:SI (match_operand:QI 1 "register_operand" "d,a")))]
  ""
  "cvtb.w %1,%0")

(define_insn "extendsfdf2"
  [(set (match_operand:DF 0 "register_operand" "=d")
	(float_extend:DF (match_operand:SF 1 "register_operand" "d")))]
  ""
  "cvts.d %1,%0")

(define_insn "truncdfsf2"
  [(set (match_operand:SF 0 "register_operand" "=d")
	(float_truncate:SF (match_operand:DF 1 "register_operand" "d")))]
  ""
  "cvtd.s %1,%0")

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
  ""
  "and #0xffff,%0")

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(zero_extend:HI (match_operand:QI 1 "register_operand" "0")))]
  ""
  "and #0xff,%0")

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
  ""
  "and #0xff,%0")

(define_insn "zero_extendsidi2"
  [(set (match_operand:DI 0 "register_operand" "=d")
	(zero_extend:DI (match_operand:SI 1 "register_operand" "0")))]
  ""
  "ld.u #0,%0")