m88k.md

早期freebsd实现

  [(set (reg:SI 3) (minus:SI (match_operand:SI 2 "register_operand" "")
			     (match_operand:SI 3 "immediate_operand" "")))
   (set (match_operand 5 "register_operand" "")
	(match_operand 4 "memory_operand" ""))
   (set (reg:SI 2) (minus:SI (match_operand:SI 1 "register_operand" "")
			     (match_dup 3)))
   (use (reg:SI 2))
   (use (reg:SI 3))
   (use (match_dup 5))
   (parallel [(set (reg:DI 2)
		   (call (mem:SI (match_operand 0 "" ""))
			 (const_int 0)))
	      (clobber (reg:SI 1))])]
  ""
  "")

;; Call an SImode looping block move library function (e.g. __movstrSI64n68).
;; operands 0-5 as in the non-looping interface
;; operand 6 is the loop count

(define_expand "call_movstrsi_loop"
  [(set (reg:SI 3) (minus:SI (match_operand:SI 2 "register_operand" "")
			     (match_operand:SI 3 "immediate_operand" "")))
   (set (match_operand:SI 5 "register_operand" "")
	(match_operand:SI 4 "memory_operand" ""))
   (set (reg:SI 2) (minus:SI (match_operand:SI 1 "register_operand" "")
			     (match_dup 3)))
   (set (reg:SI 6) (match_operand:SI 6 "immediate_operand" ""))
   (use (reg:SI 2))
   (use (reg:SI 3))
   (use (match_dup 5))
   (use (reg:SI 6))
   (parallel [(set (reg:DI 2)
		   (call (mem:SI (match_operand 0 "" ""))
			 (const_int 0)))
	      (clobber (reg:SI 1))])]
  ""
  "")

;;- zero extension instructions

(define_expand "zero_extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "")
	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[1]) == MEM
      && symbolic_address_p (XEXP (operands[1], 0)))
    operands[1]
      = legitimize_address (flag_pic, operands[1], 0, 0);
}")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
	(zero_extend:SI (match_operand:HI 1 "move_operand" "!r,n,m")))]
  "GET_CODE (operands[1]) != CONST_INT"
  "@
   mask %0,%1,0xffff
   or %0,%#r0,%h1
   %V1ld.hu %0,%1"
  [(set_attr "type" "arith,arith,load")])

(define_expand "zero_extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "")
	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[1]) == MEM
      && symbolic_address_p (XEXP (operands[1], 0)))
    operands[1]
      = legitimize_address (flag_pic, operands[1], 0, 0);
}")

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
	(zero_extend:HI (match_operand:QI 1 "move_operand" "r,n,m")))]
  "GET_CODE (operands[1]) != CONST_INT"
  "@
   mask %0,%1,0xff
   or %0,%#r0,%q1
   %V1ld.bu %0,%1"
  [(set_attr "type" "arith,arith,load")])

(define_expand "zero_extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "")
	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[1]) == MEM
      && symbolic_address_p (XEXP (operands[1], 0)))
    {
      operands[1]
	= legitimize_address (flag_pic, operands[1], 0, 0);
      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
			  gen_rtx (ZERO_EXTEND, SImode, operands[1])));
      DONE;
    }
}")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
	(zero_extend:SI (match_operand:QI 1 "move_operand" "r,n,m")))]
  "GET_CODE (operands[1]) != CONST_INT"
  "@
   mask %0,%1,0xff
   or %0,%#r0,%q1
   %V1ld.bu %0,%1"
  [(set_attr "type" "arith,arith,load")])

;;- sign extension instructions

(define_expand "extendsidi2"
  [(set (subreg:SI (match_operand:DI 0 "register_operand" "=r") 1)
        (match_operand:SI 1 "general_operand" "g"))
   (set (subreg:SI (match_dup 0) 0)
        (ashiftrt:SI (subreg:SI (match_dup 0) 1)
                     (const_int 31)))]
  ""
  "")

(define_expand "extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "")
	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[1]) == MEM
      && symbolic_address_p (XEXP (operands[1], 0)))
    operands[1]
      = legitimize_address (flag_pic, operands[1], 0, 0);
}")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
	(sign_extend:SI (match_operand:HI 1 "move_operand" "!r,P,N,m")))]
  "GET_CODE (operands[1]) != CONST_INT"
  "@
   ext %0,%1,16<0>
   or %0,%#r0,%h1
   subu %0,%#r0,%H1
   %V1ld.h %0,%1"
  [(set_attr "type" "bit,arith,arith,load")])

(define_expand "extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "")
	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[1]) == MEM
      && symbolic_address_p (XEXP (operands[1], 0)))
    operands[1]
      = legitimize_address (flag_pic, operands[1], 0, 0);
}")

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
	(sign_extend:HI (match_operand:QI 1 "move_operand" "!r,P,N,m")))]
  "GET_CODE (operands[1]) != CONST_INT"
  "@
   ext %0,%1,8<0>
   or %0,%#r0,%q1
   subu %0,%#r0,%Q1
   %V1ld.b %0,%1"
  [(set_attr "type" "bit,arith,arith,load")])

(define_expand "extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "")
	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[1]) == MEM
      && symbolic_address_p (XEXP (operands[1], 0)))
    operands[1]
      = legitimize_address (flag_pic, operands[1], 0, 0);
}")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
	(sign_extend:SI (match_operand:QI 1 "move_operand" "!r,P,N,m")))]
  "GET_CODE (operands[1]) != CONST_INT"
  "@
   ext %0,%1,8<0>
   or %0,%#r0,%q1
   subu %0,%#r0,%Q1
   %V1ld.b %0,%1"
  [(set_attr "type" "bit,arith,arith,load")])

;; Conversions between float and double.

;; The fadd instruction does not conform to IEEE 754 when used to
;; convert between float and double.  In particular, the sign of -0 is
;; not preserved.  Interestingly, fsub does conform.

(define_expand "extendsfdf2"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r")
	(float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
  "! TARGET_88110"
  "fsub.dss %0,%1,%#r0"
  [(set_attr "type" "spadd")])

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r,x")
	(float_extend:DF (match_operand:SF 1 "register_operand" "r,x")))]
  "TARGET_88110"
  "fcvt.ds %0,%1"
  [(set_attr "type" "spadd")])

(define_expand "truncdfsf2"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=r")
	(float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
  "! TARGET_88110"
  "fsub.sds %0,%1,%#r0"
  [(set_attr "type" "dpadd")])

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=r,x")
	(float_truncate:SF (match_operand:DF 1 "register_operand" "r,x")))]
  "TARGET_88110"
  "fcvt.sd %0,%1"
  [(set_attr "type" "dpadd")])

;; Conversions between floating point and integer

(define_insn "floatsidf2"
  [(set (match_operand:DF 0 "register_operand" "=r,x")
	(float:DF (match_operand:SI 1 "register_operand" "r,r")))]
  ""
  "flt.ds %0,%1"
  [(set_attr "type" "spadd,dpadd")])

(define_insn "floatsisf2"
  [(set (match_operand:SF 0 "register_operand" "=r,x")
	(float:SF (match_operand:SI 1 "register_operand" "r,r")))]
  ""
  "flt.ss %0,%1"
  [(set_attr "type" "spadd,spadd")])

(define_insn "fix_truncdfsi2"
  [(set (match_operand:SI 0 "register_operand" "=r,x")
	(fix:SI (match_operand:DF 1 "register_operand" "r,r")))]
  ""
  "trnc.sd %0,%1"
  [(set_attr "type" "dpadd,dpadd")])

(define_insn "fix_truncsfsi2"
  [(set (match_operand:SI 0 "register_operand" "=r,x")
	(fix:SI (match_operand:SF 1 "register_operand" "r,r")))]
  ""
  "trnc.ss %0,%1"
  [(set_attr "type" "spadd,dpadd")])


;;- arithmetic instructions
;;- add instructions

(define_insn "addsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(plus:SI (match_operand:SI 1 "add_operand" "%r,r")
		 (match_operand:SI 2 "add_operand" "rI,J")))]
  ""
  "@
   addu %0,%1,%2
   subu %0,%1,%n2")

;; patterns for mixed mode floating point.
;; Do not define patterns that utilize mixed mode arithmetic that result
;; in narrowing the precision, because it loses accuracy, since the standard
;; requires double rounding, whereas the 88000 instruction only rounds once.

(define_expand "adddf3"
  [(set (match_operand:DF 0 "register_operand" "=r,x")
	(plus:DF (match_operand:DF 1 "general_operand" "%r,x")
		 (match_operand:DF 2 "general_operand" "r,x")))]
  ""
  "
{
  operands[1] = legitimize_operand (operands[1], DFmode);
  operands[2] = legitimize_operand (operands[2], DFmode);
}")

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r,x")
	(plus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
		 (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
  ""
  "fadd.dss %0,%1,%2"
  [(set_attr "type" "spadd")])

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r,x")
	(plus:DF (match_operand:DF 1 "register_operand" "r,x")
		 (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
  ""
  "fadd.dds %0,%1,%2"
  [(set_attr "type" "dpadd")])

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r,x")
	(plus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
		 (match_operand:DF 2 "register_operand" "r,x")))]
  ""
  "fadd.dsd %0,%1,%2"
  [(set_attr "type" "dpadd")])

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r,x")
	(plus:DF (match_operand:DF 1 "register_operand" "%r,x")
		 (match_operand:DF 2 "register_operand" "r,x")))]
  ""
  "fadd.ddd %0,%1,%2"
  [(set_attr "type" "dpadd")])

(define_insn "addsf3"
  [(set (match_operand:SF 0 "register_operand" "=r,x")
	(plus:SF (match_operand:SF 1 "register_operand" "%r,x")
		 (match_operand:SF 2 "register_operand" "r,x")))]
  ""
  "fadd.sss %0,%1,%2"
  [(set_attr "type" "spadd")])

(define_insn ""
  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (match_operand:DI 1 "register_operand" "r")
		 (zero_extend:DI
		  (match_operand:SI 2 "register_operand" "r"))))
   (clobber (reg:CC 0))]
  ""
  "addu.co %d0,%d1,%2\;addu.ci %0,%1,%#r0"
  [(set_attr "type" "marith")])

(define_insn ""
  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (zero_extend:DI
		  (match_operand:SI 1 "register_operand" "r"))
		 (match_operand:DI 2 "register_operand" "r")))
   (clobber (reg:CC 0))]
  ""
  "addu.co %d0,%1,%d2\;addu.ci %0,%#r0,%2"
  [(set_attr "type" "marith")])

(define_insn "adddi3"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (match_operand:DI 1 "register_operand" "%r")
		 (match_operand:DI 2 "register_operand" "r")))
   (clobber (reg:CC 0))]
  ""
  "addu.co %d0,%d1,%d2\;addu.ci %0,%1,%2"
  [(set_attr "type" "marith")])

;; Add with carry insns.

(define_insn ""
  [(parallel [(set (match_operand:SI 0 "reg_or_0_operand" "=r")
		   (plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
			    (match_operand:SI 2 "reg_or_0_operand" "rO")))
	      (set (reg:CC 0)
		   (unspec:CC [(match_dup 1) (match_dup 2)] 0))])]
  ""
  "addu.co %r0,%r1,%r2")

(define_insn ""
  [(set (reg:CC 0) (unspec:CC [(match_operand:SI 0 "reg_or_0_operand" "rO")
			       (match_operand:SI 1 "reg_or_0_operand" "rO")]
			      0))]
  ""
  "addu.co %#r0,%r0,%r1")

(define_insn ""
  [(set (match_operand:SI 0 "reg_or_0_operand" "=r")
	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
		 (unspec:SI [(match_operand:SI 2 "reg_or_0_operand" "rO")
			     (reg:CC 0)] 0)))]
  ""
  "addu.ci %r0,%r1,%r2")

;;- subtract instructions

(define_insn "subsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(minus:SI (match_operand:SI 1 "register_operand" "r")
		  (match_operand:SI 2 "arith32_operand" "rI")))]
  ""
  "subu %0,%1,%2")

;; patterns for mixed mode floating point
;; Do not define patterns that utilize mixed mode arithmetic that result
;; in narrowing the precision, because it loses accuracy, since the standard
;; requires double rounding, whereas the 88000 instruction only rounds once.

(define_expand "subdf3"
  [(set (match_operand:DF 0 "register_operand" "=r,x")
	(minus:DF (match_operand:DF 1 "general_operand" "r,x")
		  (match_operand:DF 2 "general_operand" "r,x")))]
  ""
  "
{
  operands[1] = legitimize_operand (operands[1], DFmode);
  operands[2] = legitimize_operand (operands[2], DFmode);
}")

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r,x")
	(minus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
		  (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
  ""
  "fsub.dss %0,%1,%2"
  [(set_attr "type" "spadd")])

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r,x")
	(minus:DF (match_operand:DF 1 "register_operand" "r,x")
		  (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
  ""
  "fsub.dds %0,%1,%2"
  [(set_attr "type" "dpadd")])

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r,x")
	(m