m88k.md

早期freebsd实现

	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bb%L3 (31-%1),%0,%P2%P3"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else
	 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
			      (const_int 1)
			      (match_operand:SI 1 "int5_operand" ""))
	     (const_int 0))
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bb%L2 (31-%1),%0,%P2%P3"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else
	 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
			      (const_int 1)
			      (match_operand:SI 1 "int5_operand" ""))
	     (const_int 0))
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bb%L3 (31-%1),%0,%P2%P3"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else
	 (eq (and:SI (match_operand:SI 0 "reg_or_bbx_mask_operand" "%r")
		     (match_operand:SI 1 "reg_or_bbx_mask_operand" "n"))
	      (const_int 0))
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  "(GET_CODE (operands[0]) == CONST_INT)
   != (GET_CODE (operands[1]) == CONST_INT)"
  "bb%L3 %p1,%0,%P2%P3"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else
	 (ne (and:SI (match_operand:SI 0 "reg_or_bbx_mask_operand" "%r")
		     (match_operand:SI 1 "reg_or_bbx_mask_operand" "n"))
	     (const_int 0))
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  "(GET_CODE (operands[0]) == CONST_INT)
   != (GET_CODE (operands[1]) == CONST_INT)"
  "bb%L2 %p1,%0,%P2%P3"
  [(set_attr "type" "branch")])

;; The comparison operations store the comparison into a register and
;; record that register.  The following Bxx or Sxx insn uses that
;; register as an input.  To facilitate use of bcnd instead of cmp/bb1,
;; cmpsi records it's operands and produces no code when any operand
;; is constant.  In this case, the Bxx insns use gen_bcnd and the
;; Sxx insns use gen_test to ensure a cmp has been emitted.
;;
;; This could also be done for SFmode and DFmode having only beq and bne
;; use gen_bcnd.  The others must signal NaNs.  It seems though that zero
;; has already been copied into a register.
;;
;; cmpsi/beq and cmpsi/bne can always be done with bcnd if any operand
;; is a constant.  (This idea is due to Torbjorn Granlund.)  Others can
;; use bcnd only if an operand is zero.
;;
;; It is necessary to distinguish a register holding condition codes.
;; This is done by context.

(define_expand "test"
  [(set (match_dup 2)
	(compare:CC (match_operand 0 "" "")
		    (match_operand 1 "" "")))]
  ""
  "
{
  if (m88k_compare_reg)
    abort ();

  if (GET_CODE (operands[0]) == CONST_INT
      && ! SMALL_INT (operands[0]))
    operands[0] = force_reg (SImode, operands[0]);

  if (GET_CODE (operands[1]) == CONST_INT
      && ! SMALL_INT (operands[1]))
    operands[1] = force_reg (SImode, operands[1]);

  operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode);
}")

; @@ The docs say don't do this.  It's probably a nop since the insn looks
; identical to cmpsi against zero.  Is there an advantage to providing
; this, perhaps with a different form?

;(define_expand "tstsi"
;  [(set (match_dup 1)
;	(compare:CC (match_operand:SI 0 "register_operand" "")
;		    (const_int 0)))]
; ""
; "
;{
;  m88k_compare_reg = 0;
;  m88k_compare_op0 = operands[0];
;  m88k_compare_op1 = const0_rtx;
;  DONE;
;}")

(define_expand "cmpsi"
  [(set (match_dup 2)
	(compare:CC (match_operand:SI 0 "register_operand" "")
		    (match_operand:SI 1 "arith32_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[0]) == CONST_INT
      || GET_CODE (operands[1]) == CONST_INT)
    {
      m88k_compare_reg = 0;
      m88k_compare_op0 = operands[0];
      m88k_compare_op1 = operands[1];
      DONE;
    }
  operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode);
}")

(define_expand "cmpsf"
  [(set (match_dup 2)
	(compare:CC (match_operand:SF 0 "register_operand" "")
		    (match_operand:SF 1 "register_operand" "")))]
  ""
  "operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode);")

(define_expand "cmpdf"
  [(set (match_dup 2)
	(compare:CC (match_operand:DF 0 "general_operand" "")
		    (match_operand:DF 1 "general_operand" "")))]
  ""
  "
{
  operands[0] = legitimize_operand (operands[0], DFmode);
  operands[1] = legitimize_operand (operands[1], DFmode);
  operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode);
}")

; @@ Get back to this later on.
;
;(define_insn "cmpdi"
;  [(set (cc0)
;	(compare:CC (match_operand:DI 0 "register_operand" "r")
;		    (match_operand:DI 1 "register_operand" "r")))]
;  ""
;  "*
;{
;  if ((cc_status.mdep & MDEP_LS_CHANGE) != 0)
;    abort ();	/* output_move_double MDEP_LS_CHANGE bits were set. */
;
;  cc_status.mdep &= ~ MDEP_LS_MASK;
;
;  operands[2] = gen_label_rtx ();
;  /* Remember, %! is the condition code register and %@ is the
;     literal synthesis register.  */
;
;  output_asm_insn (\"cmp %!,%0,%1\;bb0 %#eq,%!,%l2\;cmp %!,%d0,%d1\",
;		   operands);
;
;  output_asm_insn (\"extu %@,%!,4<8>\;clr %!,%!,4<4>\", operands);
;  output_asm_insn (\"mak %@,%@,4<4>\;or %!,%!,%@\", operands);
;  output_label (XINT (operands[2], 3));
;  return \"\";
;}"

;; The actual compare instructions.

(define_insn ""
  [(set (match_operand:CC 0 "register_operand" "=r")
	(compare:CC (match_operand:SI 1 "register_operand" "rO")
		    (match_operand:SI 2 "arith_operand" "rI")))]
  ""
  "cmp %0,%r1,%2")

(define_insn ""
  [(set (match_operand:CC 0 "register_operand" "=r,r,r,r")
	(compare:CC (match_operand:SF 1 "register_operand" "r,r,x,x")
		    (match_operand:SF 2 "real_or_0_operand" "r,G,x,G")))]
  ""
  "@
   fcmp.sss %0,%1,%2
   fcmp.sss %0,%1,%#r0
   fcmp.sss %0,%1,%2
   fcmp.sss %0,%1,%#x0"
  [(set_attr "type" "spcmp")])

(define_insn ""
  [(set (match_operand:CC 0 "register_operand" "=r,r")
	(compare:CC (match_operand:DF 1 "register_operand" "r,x")
		    (float_extend:DF
		     (match_operand:SF 2 "register_operand" "r,x"))))]
  ""
  "fcmp.sds %0,%1,%2"
  [(set_attr "type" "dpcmp")])

(define_insn ""
  [(set (match_operand:CC 0 "register_operand" "=r,r")
	(compare:CC (float_extend:DF
		     (match_operand:SF 1 "register_operand" "r,x"))
		    (match_operand:DF 2 "register_operand" "r,x")))]
  ""
  "fcmp.ssd %0,%1,%2"
  [(set_attr "type" "dpcmp")])

(define_insn ""
  [(set (match_operand:CC 0 "register_operand" "=r,r,r,r")
	(compare:CC (match_operand:DF 1 "register_operand" "r,r,x,x")
		    (match_operand:DF 2 "real_or_0_operand" "r,G,x,G")))]
  ""
  "@
   fcmp.sdd %0,%1,%2
   fcmp.sds %0,%1,%#r0
   fcmp.sdd %0,%1,%2
   fcmp.sds %0,%1,%#x0"
  [(set_attr "type" "dpcmp")])

;; Store condition code insns.  The compare insns set a register
;; rather than cc0 and record that register for use here.  See above
;; for the special treatment of cmpsi with a constant operand.

;; @@ For the m88110, use fcmpu for bxx sxx inequality comparisons.

(define_expand "seq"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (EQ, SImode);")

(define_expand "sne"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (NE, SImode);")

(define_expand "sgt"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (GT, SImode);")

(define_expand "sgtu"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (GTU, SImode);")

(define_expand "slt"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (LT, SImode);")

(define_expand "sltu"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (LTU, SImode);")

(define_expand "sge"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (GE, SImode);")

(define_expand "sgeu"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (GEU, SImode);")

(define_expand "sle"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (LE, SImode);")

(define_expand "sleu"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (LEU, SImode);")

;; The actual set condition code instruction.

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(match_operator:SI 1 "relop"
			   [(match_operand:CC 2 "register_operand" "r")
			    (const_int 0)]))]
  ""
  "ext %0,%2,1<%C1>"
  [(set_attr "type" "bit")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(neg:SI
	 (match_operator:SI 1 "relop"
			    [(match_operand:CC 2 "register_operand" "r")
			     (const_int 0)])))]
  ""
  "extu %0,%2,1<%C1>"
  [(set_attr "type" "bit")])

;; Conditional branch insns.  The compare insns set a register
;; rather than cc0 and record that register for use here.  See above
;; for the special case of cmpsi with a constant operand.

(define_expand "bcnd"
  [(set (pc)
	(if_then_else (match_operand 0 "" "")
		      (label_ref (match_operand 1 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg) abort ();")

(define_expand "bxx"
  [(set (pc)
	(if_then_else (match_operand 0 "" "")
		      (label_ref (match_operand 1 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0) abort ();")

(define_expand "beq"
  [(set (pc)
	(if_then_else (eq (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_bcnd (EQ, operands[0]);
       DONE;
     }
   operands[1] = m88k_compare_reg;")

(define_expand "bne"
  [(set (pc)
	(if_then_else (ne (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_bcnd (NE, operands[0]);
       DONE;
     }
   operands[1] = m88k_compare_reg;")

(define_expand "bgt"
  [(set (pc)
	(if_then_else (gt (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_bcnd (GT, operands[0]);
       DONE;
     }
   operands[1] = m88k_compare_reg;")

(define_expand "bgtu"
  [(set (pc)
	(if_then_else (gtu (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_jump_insn (gen_bxx (emit_test (GTU, VOIDmode), operands[0]));
       DONE;
     }
   operands[1] = m88k_compare_reg;")

(define_expand "blt"
  [(set (pc)
	(if_then_else (lt (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_bcnd (LT, operands[0]);
       DONE;
     }
   operands[1] = m88k_compare_reg;")

(define_expand "bltu"
  [(set (pc)
	(if_then_else (ltu (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_jump_insn (gen_bxx (emit_test (LTU, VOIDmode), operands[0]));
       DONE;
     }
   operands[1] = m88k_compare_reg;")

(define_expand "bge"
  [(set (pc)
	(if_then_else (ge (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_bcnd (GE, operands[0]);
       DONE;
     }
   operands[1] = m88k_compare_reg;")

(define_expand "bgeu"
  [(set (pc)
	(if_then_else (geu (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_jump_insn (gen_bxx (emit_test (GEU, VOIDmode), operands[0]));