m88k.md

早期freebsd实现

   if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
     ; /* The conditions match.  */
   else if (GET_CODE (operands[1])
	    == reverse_condition (GET_CODE (operands[3])))
     /* Reverse the condition by complimenting the compare word.  */
     operands[4] = gen_rtx (NOT, CCmode, operands[4]);
   else
     {
       /* Make the condition pairs line up by rotating the compare word.  */
       int cv1 = condition_value (operands[1]);
       int cv2 = condition_value (operands[3]);

       operands[4] = gen_rtx (ROTATE, CCmode, operands[4],
			      gen_rtx (CONST_INT, VOIDmode,
				       ((cv2 & ~1) - (cv1 & ~1)) & 0x1f));
       /* Reverse the condition if needed.  */
       if ((cv1 & 1) != (cv2 & 1))
	 operands[4] = gen_rtx (NOT, CCmode, operands[4]);
     }")

(define_split
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ior:SI (match_operator 1 "relop"
				[(match_operand:CC 2 "register_operand" "%r")
				 (const_int 0)])
		(match_operator 3 "relop"
				[(match_operand:CC 4 "register_operand" "r")
				 (const_int 0)])))
   (clobber (match_operand:SI 5 "register_operand" "=r"))]
  "GET_CODE (operands[1]) == GET_CODE (operands[3])
   || GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
  [(set (match_dup 5)
	(ior:CC (match_dup 4)
		(match_dup 2)))
   (set (match_dup 0)
	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
  "operands[5] = gen_rtx (SUBREG, CCmode, operands[5], 0);
   /* Reverse the condition by  complimenting the compare word.  */
   if (GET_CODE (operands[1]) != GET_CODE (operands[3]))
      operands[4] = gen_rtx (NOT, CCmode, operands[4]);")

(define_split
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (neg:SI 
		 (match_operator 1 "relop"
				 [(match_operand:CC 2 "register_operand" "%r")
				  (const_int 0)]))
		(neg:SI
		 (match_operator 3 "relop"
				 [(match_operand:CC 4 "register_operand" "r")
				  (const_int 0)]))))
   (clobber (match_operand:SI 5 "register_operand" "=r"))]
  ""
  [(set (match_dup 5)
	(and:CC (match_dup 4)
		(match_dup 2)))
   (set (match_dup 0)
	(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
  "operands[5] = gen_rtx (SUBREG, CCmode, operands[5], 0);
   if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
     ; /* The conditions match.  */
   else if (GET_CODE (operands[1])
	    == reverse_condition (GET_CODE (operands[3])))
     /* Reverse the condition by complimenting the compare word.  */
     operands[4] = gen_rtx (NOT, CCmode, operands[4]);
   else
     {
       /* Make the condition pairs line up by rotating the compare word.  */
       int cv1 = condition_value (operands[1]);
       int cv2 = condition_value (operands[3]);

       operands[4] = gen_rtx (ROTATE, CCmode, operands[4],
			      gen_rtx (CONST_INT, VOIDmode,
				       ((cv2 & ~1) - (cv1 & ~1)) & 0x1f));
       /* Reverse the condition if needed.  */
       if ((cv1 & 1) != (cv2 & 1))
	 operands[4] = gen_rtx (NOT, CCmode, operands[4]);
     }")

(define_split
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (match_operator 1 "relop"
				[(match_operand:CC 2 "register_operand" "%r")
				 (const_int 0)])
		(match_operator 3 "relop"
				[(match_operand:CC 4 "register_operand" "r")
				 (const_int 0)])))
   (clobber (match_operand:SI 5 "register_operand" "=r"))]
  "GET_CODE (operands[1]) == GET_CODE (operands[3])
   || GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
  [(set (match_dup 5)
	(and:CC (match_dup 4)
		(match_dup 2)))
   (set (match_dup 0)
	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
  "operands[5] = gen_rtx (SUBREG, CCmode, operands[5], 0);
   /* Reverse the condition by  complimenting the compare word.  */
   if (GET_CODE (operands[1]) != GET_CODE (operands[3]))
      operands[4] = gen_rtx (NOT, CCmode, operands[4]);")

;; Logical operations on compare words.

(define_insn ""
  [(set (match_operand:CC 0 "register_operand" "=r")
	(and:CC (not:CC (match_operand:CC 1 "register_operand" "r"))
		(match_operand:CC 2 "register_operand" "r")))]
  ""
  "and.c %0,%2,%1")


(define_insn ""
  [(set (match_operand:CC 0 "register_operand" "=r")
	(and:CC (match_operand:CC 1 "register_operand" "%r")
		(match_operand:CC 2 "register_operand" "r")))]
  ""
  "and %0,%1,%2")

(define_insn ""
  [(set (match_operand:CC 0 "register_operand" "=r")
	(ior:CC (not:CC (match_operand:CC 1 "register_operand" "r"))
		(match_operand:CC 2 "register_operand" "r")))]
  ""
  "or.c %0,%2,%1")

(define_insn ""
  [(set (match_operand:CC 0 "register_operand" "=r")
	(ior:CC (match_operand:CC 1 "register_operand" "%r")
		(match_operand:CC 2 "register_operand" "r")))]
  ""
  "or %0,%1,%2")

(define_insn ""
  [(set (match_operand:CC 0 "register_operand" "=r")
	(rotate:CC (match_operand:CC 1 "register_operand" "r")
		   (match_operand:CC 2 "int5_operand" "")))]
  ""
  "rot %0,%1,%2"
  [(set_attr "type" "bit")])

;; rotate/and[.c] and rotate/ior[.c]

(define_split
  [(set (match_operand:CC 0 "register_operand" "=r")
	(ior:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
			   (match_operand:CC 2 "int5_operand" ""))
		(match_operand:CC 3 "register_operand" "r")))
   (clobber (match_operand:CC 4 "register_operand" "=r"))]
  ""
  [(set (match_dup 4)
	(rotate:CC (match_dup 1) (match_dup 2)))
   (set (match_dup 0)
	(ior:CC (match_dup 4) (match_dup 3)))]
  "")

(define_insn ""
  [(set (match_operand:CC 0 "register_operand" "=r")
	(ior:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
			   (match_operand:CC 2 "int5_operand" ""))
		(match_operand:CC 3 "register_operand" "r")))
   (clobber (match_scratch:CC 4 "=r"))]
  ""
  "#")

(define_split
  [(set (match_operand:CC 0 "register_operand" "=r")
	(ior:CC (not:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
				   (match_operand:CC 2 "int5_operand" "")))
		(match_operand:CC 3 "register_operand" "r")))
   (clobber (match_operand:CC 4 "register_operand" "=r"))]
  ""
  [(set (match_dup 4)
	(rotate:CC (match_dup 1) (match_dup 2)))
   (set (match_dup 0)
	(ior:CC (not:CC (match_dup 4)) (match_dup 3)))]
  "")

(define_insn ""
  [(set (match_operand:CC 0 "register_operand" "=r")
	(ior:CC (not:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
				   (match_operand:CC 2 "int5_operand" "")))
		(match_operand:CC 3 "register_operand" "r")))
   (clobber (match_scratch:CC 4 "=r"))]
  ""
  "#")

(define_split
  [(set (match_operand:CC 0 "register_operand" "=r")
	(and:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
			   (match_operand:CC 2 "int5_operand" ""))
		(match_operand:CC 3 "register_operand" "r")))
   (clobber (match_operand:CC 4 "register_operand" "=r"))]
  ""
  [(set (match_dup 4)
	(rotate:CC (match_dup 1) (match_dup 2)))
   (set (match_dup 0)
	(and:CC (match_dup 4) (match_dup 3)))]
  "")

(define_insn ""
  [(set (match_operand:CC 0 "register_operand" "=r")
	(and:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
			   (match_operand:CC 2 "int5_operand" ""))
		(match_operand:CC 3 "register_operand" "r")))
   (clobber (match_scratch:CC 4 "=r"))]
  ""
  "#")

(define_split
  [(set (match_operand:CC 0 "register_operand" "=r")
	(and:CC (not:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
				   (match_operand:CC 2 "int5_operand" "")))
		(match_operand:CC 3 "register_operand" "r")))
   (clobber (match_operand:CC 4 "register_operand" "=r"))]
  ""
  [(set (match_dup 4)
	(rotate:CC (match_dup 1) (match_dup 2)))
   (set (match_dup 0)
	(and:CC (not:CC (match_dup 4)) (match_dup 3)))]
  "")

(define_insn ""
  [(set (match_operand:CC 0 "register_operand" "=r")
	(and:CC (not:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
				   (match_operand:CC 2 "int5_operand" "")))
		(match_operand:CC 3 "register_operand" "r")))
   (clobber (match_scratch:CC 4 "=r"))]
  ""
  "#")

;; Recognize bcnd instructions for integer values.  This is distinguished
;; from a conditional branch instruction (below) with SImode instead of
;; CCmode.

(define_insn ""
  [(set (pc)
	(if_then_else
	 (match_operator 0 "relop_no_unsigned"
			 [(match_operand:SI 1 "register_operand" "r")
			  (const_int 0)])
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bcnd%. %R3%B0,%1,%P2%P3"
  [(set_attr "type" "branch")])

;; Recognize tests for sign and zero.

(define_insn ""
  [(set (pc)
	(if_then_else
	 (match_operator 0 "equality_op"
			 [(match_operand:SI 1 "register_operand" "r")
			  (const_int -2147483648)])
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bcnd%. %R3%E0,%1,%P2%P3"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else
	 (match_operator 0 "equality_op"
			 [(zero_extract:SI
			   (match_operand:SI 1 "register_operand" "r")
			   (const_int 31)
			   (const_int 1))
			  (const_int 0)])
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bcnd%. %R3%D0,%1,%P2%P3"
  [(set_attr "type" "branch")])

;; Recognize bcnd instructions for double integer values

(define_insn ""
  [(set (pc)
	(if_then_else
	 (match_operator 0 "relop_no_unsigned"
			 [(sign_extend:DI
			   (match_operand:SI 1 "register_operand" "r"))
			  (const_int 0)])
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bcnd%. %R3%B0,%1,%P2%P3"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else
	 (match_operator 0 "equality_op"
			 [(zero_extend:DI
			   (match_operand:SI 1 "register_operand" "r"))
			  (const_int 0)])
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bcnd%. %R3%B0,%1,%P2%P3"
  [(set_attr "type" "branch")])

; @@ I doubt this is interesting until cmpdi is provided.  Anyway, it needs
; to be reworked.
;
;(define_insn ""
;  [(set (pc)
;	(if_then_else
;	 (match_operator 0 "relop_no_unsigned"
;			 [(match_operand:DI 1 "register_operand" "r")
;			  (const_int 0)])
;	 (match_operand 2 "pc_or_label_ref" "")
;	 (match_operand 3 "pc_or_label_ref" "")))]
;  ""
;  "*
;{
;  switch (GET_CODE (operands[0]))
;    {
;    case EQ:
;    case NE:
;      /* I'm not sure if it's safe to use .n here.  */
;      return \"or %!,%1,%d1\;bcnd %R3%B0,%!,%P2%P3\";
;    case GE:
;    case LT:
;      return \"bcnd%. %R3%B0,%1,%P2%P3\";
;    case GT:
;      {
;	rtx op2 = operands[2];
;	operands[2] = operands[3];
;	operands[3] = op2;
;      }
;    case LE:
;      if (GET_CODE (operands[3]) == LABEL_REF)
;	{
;	  int label_num;
;	  operands[2] = gen_label_rtx ();
;	  label_num = XINT (operands[2], 3);
;	  output_asm_insn
;	    (\"bcnd%. %#lt0,%1,%2\;or %!,%1,%d1\;bcnd %#ne0,%!,%3\", operands);
;	  output_label (label_num);
;	  return \"\";
;	}
;      else
;	return \"bcnd%. %#lt0,%1,%2\;or %!,%1,%d1\;bcnd %#eq0,%!,%2\";
;    }
;}")

;; Recognize bcnd instructions for single precision float values
;; Exclude relational operations as they must signal NaNs.

;; @@ These bcnd insns for float and double values don't seem to be recognized.

(define_insn ""
  [(set (pc)
	(if_then_else
	 (match_operator 0 "equality_op"
			 [(float_extend:DF
			   (match_operand:SF 1 "register_operand" "r"))
			  (const_int 0)])
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bcnd%. %R3%D0,%1,%P2%P3"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else
	 (match_operator 0 "equality_op"
			 [(match_operand:SF 1 "register_operand" "r")
			  (const_int 0)])
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bcnd%. %R3%D0,%1,%P2%P3"
  [(set_attr "type" "branch")])

;; Recognize bcnd instructions for double precision float values
;; Exclude relational operations as they must signal NaNs.

(define_insn ""
  [(set (pc)
	(if_then_else
	 (match_operator 0 "equality_op"
			 [(match_operand:DF 1 "register_operand" "r")
			  (const_int 0)])
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "*
{
  int label_num;

  if (GET_CODE (operands[0]) == NE)
    {
      rtx op2 = operands[2];
      operands[2] = operands[3];
      operands[3] = op2;
    }
  if (GET_CODE (operands[3]) == LABEL_REF)
    return \"bcnd%. 0x5,%1,%3\;bcnd %#ne0,%d1,%3\";

  operands[3] = gen_label_rtx ();
  label_num = XINT (operands[3], 3);
  output_asm_insn (\"bcnd%. 0x5,%1,%3\;bcnd %#eq0,%d1,%2\", operands);
  output_label (label_num);
  return \"\";
}"
  [(set_attr "type" "branch")])

;; Recognize bb0 and bb1 instructions.  These use two unusual template
;; patterns, %Lx and %Px.  %Lx outputs a 1 if operand `x' is a LABEL_REF
;; otherwise it outputs a 0.  It then may print ".n" if the delay slot
;; is used.  %Px does noting if `x' is PC and outputs the operand if `x'
;; is a LABEL_REF.

(define_insn ""
  [(set (pc)
	(if_then_else
	 (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
			      (const_int 1)
			      (match_operand:SI 1 "int5_operand" ""))
	     (const_int 0))
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bb%L2 (31-%1),%0,%P2%P3"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else
	 (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
			      (const_int 1)
			      (match_operand:SI 1 "int5_operand" ""))
	     (const_int 0))