arm.md

早期freebsd实现

		 (neg:SI (match_operand:SI 1 "arm_rhs_operand" "rI"))))]
  ""
  "*
  return (arm_output_asm_insn (\"cmn\\t%0, %1\", operands));
")

(define_insn "cmpsf"
  [(set (cc0)
	(compare (match_operand:SF 0 "register_operand" "f")
		 (match_operand:SF 1 "fpu_rhs_operand" "fG")))]
  ""
  "*
  return (arm_output_asm_insn (\"cmf\\t%0, %1\", operands));
")

(define_insn "cmpdf"
  [(set (cc0)
	(compare (match_operand:DF 0 "register_operand" "f")
		 (match_operand:DF 1 "fpu_rhs_operand" "fG")))]
  ""
  "*
  return (arm_output_asm_insn (\"cmf\\t%0, %1\", operands));
")

;; Conditional branch insns

(define_insn "beq"
  [(set (pc)
	(if_then_else (eq (cc0) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
  return (arm_output_asm_insn (\"beq\\t%l0\", operands));
")

(define_insn "bne"
  [(set (pc)
	(if_then_else (ne (cc0) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
  return (arm_output_asm_insn (\"bne\\t%l0\", operands));
")

(define_insn "bgt"
  [(set (pc)
	(if_then_else (gt (cc0) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
  return (arm_output_asm_insn (\"bgt\\t%l0\", operands));
")

(define_insn "ble"
  [(set (pc)
	(if_then_else (le (cc0) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
  return (arm_output_asm_insn (\"ble\\t%l0\", operands));
")

(define_insn "bge"
  [(set (pc)
	(if_then_else (ge (cc0) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
  return (arm_output_asm_insn (\"bge\\t%l0\", operands));
")

(define_insn "blt"
  [(set (pc)
	(if_then_else (lt (cc0) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
  return (arm_output_asm_insn (\"blt\\t%l0\", operands));
")

(define_insn "bgtu"
  [(set (pc)
	(if_then_else (gtu (cc0) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
  return (arm_output_asm_insn (\"bhi\\t%l0\", operands));
")

(define_insn "bleu"
  [(set (pc)
	(if_then_else (leu (cc0) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
  return (arm_output_asm_insn (\"bls\\t%l0\", operands));
")

(define_insn "bgeu"
  [(set (pc)
	(if_then_else (geu (cc0) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
  return (arm_output_asm_insn (\"bhs\\t%l0\", operands));
")

(define_insn "bltu"
  [(set (pc)
	(if_then_else (ltu (cc0) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
  return (arm_output_asm_insn (\"blo\\t%l0\", operands));
")

;; Inverted conditional branch insns

(define_insn ""
  [(set (pc)
	(if_then_else (eq (cc0) (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "*
  return (arm_output_asm_insn (\"bne\\t%l0\", operands));
")

(define_insn ""
  [(set (pc)
	(if_then_else (ne (cc0) (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "*
  return (arm_output_asm_insn (\"beq\\t%l0\", operands));
")

(define_insn ""
  [(set (pc)
	(if_then_else (gt (cc0) (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "*
  return (arm_output_asm_insn (\"ble\\t%l0\", operands));
")

(define_insn ""
  [(set (pc)
	(if_then_else (le (cc0) (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "*
  return (arm_output_asm_insn (\"bgt\\t%l0\", operands));
")

(define_insn ""
  [(set (pc)
	(if_then_else (ge (cc0) (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "*
  return (arm_output_asm_insn (\"blt\\t%l0\", operands));
")

(define_insn ""
  [(set (pc)
	(if_then_else (lt (cc0) (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "*
  return (arm_output_asm_insn (\"bge\\t%l0\", operands));
")

(define_insn ""
  [(set (pc)
	(if_then_else (gtu (cc0) (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "*
  return (arm_output_asm_insn (\"bls\\t%l0\", operands));
")

(define_insn ""
  [(set (pc)
	(if_then_else (leu (cc0) (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "*
  return (arm_output_asm_insn (\"bhi\\t%l0\", operands));
")

(define_insn ""
  [(set (pc)
	(if_then_else (geu (cc0) (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "*
  return (arm_output_asm_insn (\"blo\\t%l0\", operands));
")

(define_insn ""
  [(set (pc)
	(if_then_else (ltu (cc0) (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "*
  return (arm_output_asm_insn (\"bhs\\t%l0\", operands));
")

;; Jump and linkage insns
;; `return' is still a jump-to-epilogue...

(define_insn "jump"
  [(set (pc)
	(label_ref (match_operand 0 "" "")))]
  ""
  "*
  return (arm_output_asm_insn (\"b\\t%l0\", operands));
")

(define_insn "call"
  [(call (match_operand 0 "memory_operand" "m")
	 (match_operand 1 "general_operand" "g"))
   (clobber (reg:SI 14))]
  ""
  "*
  return (output_call (operands));
")

(define_insn "call_value"
  [(set (match_operand 0 "" "=rf")
	(call (match_operand 1 "memory_operand" "m")
	(match_operand 2 "general_operand" "g")))
   (clobber (reg:SI 14))]
  ""
  "*
  return (output_call (&operands[1]));
")

;; Allow calls to SYMBOL_REFs specially as they are not valid general addresses
;; The 'a' causes the operand to be treated as an address, i.e. no '#' output.

(define_insn ""
  [(call (mem:SI (match_operand:SI 0 "" "i"))
	 (match_operand:SI 1 "general_operand" "g"))
   (clobber (reg:SI 14))]
  "GET_CODE (operands[0]) == SYMBOL_REF"
  "*
  return (arm_output_asm_insn (\"bl\\t%a0\", operands));
")

(define_insn ""
  [(set (match_operand 0 "register_operand" "=rf")
	(call (mem:SI (match_operand:SI 1 "" "i"))
	(match_operand:SI 2 "general_operand" "g")))
   (clobber (reg:SI 14))]
  "GET_CODE(operands[1]) == SYMBOL_REF"
  "*
  return (arm_output_asm_insn (\"bl\\t%a1\", operands));
")

(define_insn "tablejump"
  [(set (pc)
	(match_operand:SI 0 "register_operand" "r"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "*
  return (arm_output_asm_insn (\"mov\\tpc, %0\\t@ table jump, label %l1\", operands));
")

(define_insn "indirect_jump"
  [(set (pc)
	(match_operand:SI 0 "register_operand" "r"))]
  ""
  "*
  return (arm_output_asm_insn (\"mov\\tpc, %0\\t@ indirect jump\", operands));
")

;; Misc insns

(define_insn "nop"
  [(const_int 0)]
  ""
  "*
  return (arm_output_asm_insn (\"mov\\tr0, r0\\t@ nop\", operands));
")

;; Patterns to allow combination of arithmetic, cond code and shifts

;(define_insn ""
;  [(set (match_operand:SI 0 "register_operand" "=r")
;        (match_operator:SI 1 "shiftable_operator"
;          [(match_operand:SI 2 "register_operand" "r")
;           (match_operator:SI 3 "shift_operator"
;             [(match_operand:SI 4 "register_operand" "r")
;	      (match_operand:SI 5 "nonmemory_operand" "rn")])]))]
;  ""
;  "*
;  return (output_arithmetic_with_shift (operands, FALSE, FALSE));
;  "
;)

;(define_insn ""
;  [(set (match_operand:SI 0 "register_operand" "=r")
;        (match_operator:SI 1 "shiftable_operator"
;          [(match_operator:SI 3 "shift_operator"
;             [(match_operand:SI 4 "register_operand" "r")
;              (match_operand:SI 5 "nonmemory_operand" "rI")])
;           (match_operand:SI 2 "register_operand" "r")]))]
;  ""
;  "*
;  return (output_arithmetic_with_shift (operands, TRUE, FALSE));
;")

;; Patterns to allow combination of arithmetic and multiplication

;(define_insn ""
;  [(set (match_operand:SI 0 "register_operand" "=r")
;        (match_operator:SI 1 "shiftable_operator"
;          [(match_operand:SI 2 "register_operand" "r")
;             (mult:SI
;               (match_operand:SI 3 "register_operand" "r")
;               (match_operand:SI 4 "power_of_two_operand" "n"))]))]
;  ""
;  "*
;  return (output_arithmetic_with_immediate_multiply (operands, FALSE));
;")

; Uncomment this to show combiner problem (see ../COMBINER-PROBLEM).
;(define_insn ""
;  [(set (match_operand:SI 0 "register_operand" "=r")
;        (match_operator:SI 1 "shiftable_operator"
;	  [(mult:SI
;	    (match_operand:SI 3 "register_operand" "r")
;	    (match_operand:SI 4 "power_of_two_operand" "n"))
;	   (match_operand:SI 2 "register_operand" "r")]))]
;  ""
;  "*
;  return (output_arithmetic_with_immediate_multiply (operands, TRUE));
;")

;; Peephole optimizations.

;; When testing a bitset smaller than 9 bits for (un)equality, a
;; shift/and/cmp/b{eq,ne} sequence can be replaced by one tst and the same
;; branch sequence.

;;(define_peephole
;;  [(set (match_operand:SI 0 "register_operand" "=r")
;;	(lshiftrt:SI (match_dup 0)
;;		     (match_operand 1 "immediate_operand" "")))
;;   (set (match_dup 0)
;;	(and:SI (match_dup 0)
;;		(match_operand 2 "immediate_operand" "")))
;;   (set (cc0) (match_dup 0))
;;   (set (pc)
;;	(if_then_else (ne (cc0) (const_int 0))
;;		      (label_ref (match_operand 3 "" ""))
;;		      (pc)))]
;;  "dead_or_set_p (PREV_INSN (insn), operands[0])
;;   && GET_CODE (operands[2]) == CONST_INT && GET_CODE (operands[1]) == CONST_INT
;;   && const_ok_for_arm (INTVAL (operands[2]) << INTVAL (operands[1]))"
;;  "*
;;  operands[2] = gen_rtx (CONST_INT, VOIDmode,
;;                         INTVAL (operands[2]) << INTVAL (operands[1]));
;;  arm_output_asm_insn (\"tst\\t%0, %2\\t\\t@ ph test bitfield\", operands);
;;  return (arm_output_asm_insn (\"bne\\t%l3\", operands));
;;")

;;(define_peephole
;;  [(set (match_operand:SI 0 "register_operand" "=r")
;;	(lshiftrt:SI (match_dup 0)
;;		     (match_operand 1 "immediate_operand" "")))
;;   (set (match_dup 0)
;;	(and:SI (match_dup 0)
;;		(match_operand 2 "immediate_operand" "")))
;;   (set (cc0) (match_dup 0))
;;   (set (pc)
;;	(if_then_else (ne (cc0) (const_int 0))
;;		      (pc)
;;		      (label_ref (match_operand 3 "" ""))))]
;;  "dead_or_set_p (prev_real_insn (insn), operands[0])
;;   && GET_CODE (operands[2]) == CONST_INT && GET_CODE (operands[1]) == CONST_INT
;;   && const_ok_for_arm (INTVAL (operands[2]) << INTVAL (operands[1]))"
;;  "*
;;  operands[2] = gen_rtx (CONST_INT, VOIDmode,
;;                         INTVAL (operands[2]) << INTVAL (operands[1]));
;;  arm_output_asm_insn (\"tst\\t%0, %2\\t\\t@ ph test bitfield\", operands);
;;  return (arm_output_asm_insn (\"beq\\t%l3\", operands));
;;")

;; This allows negative constants to be compared since GCC appears not to try
;; converting them with a NEG.

;;(define_peephole
;;  [(set (match_operand:SI 2 "register_operand" "=r")
;;        (match_operand:SI 1 "immediate_operand" "n"))
;;   (set (cc0)
;;        (compare (match_operand:SI 0 "register_operand" "r")
;;                 (match_dup 1)))]
;;  "const_ok_for_arm (-INTVAL (operands[1]))
;;   && dead_or_set_p (prev_real_insn (insn), operands[0])"
;;  "*
;;  operands[1] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[1]));
;;  return (arm_output_asm_insn (\"cmn\\t%0, %1\\t\\t@ ph negate comparison\", operands));
;;")

;; Local variables:
;; mode:emacs-lisp
;; eval: (setq comment-start ";; ")
;; eval: (setq comment-end "")
;; eval: (setq comment-start-skip ";;+ *")
;; eval: (set-syntax-table (copy-sequence (syntax-table)))
;; eval: (modify-syntax-entry ?[ "(]")
;; eval: (modify-syntax-entry ?] ")[")
;; eval: (modify-syntax-entry ?{ "(}")
;; eval: (modify-syntax-entry ?} "){")
;; End: