rs6000.md

早期freebsd实现

}"
  [(set_attr "type" "fp")])

(define_insn "negsf2"
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
	(neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
  ""
  "fneg %0,%1"
  [(set_attr "type" "fp")])

(define_insn "abssf2"
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
	(abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
  ""
  "fabs %0,%1"
  [(set_attr "type" "fp")])

(define_insn ""
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
	(neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
  ""
  "fnabs %0,%1"
  [(set_attr "type" "fp")])

(define_insn "addsf3"
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
	(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
		 (match_operand:SF 2 "gpc_reg_operand" "f")))]
  ""
  "fa %0,%1,%2"
  [(set_attr "type" "fp")])

(define_insn "subsf3"
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
	(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
		  (match_operand:SF 2 "gpc_reg_operand" "f")))]
  ""
  "fs %0,%1,%2"
  [(set_attr "type" "fp")])

(define_insn "mulsf3"
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
	(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
		 (match_operand:SF 2 "gpc_reg_operand" "f")))]
  ""
  "fm %0,%1,%2"
  [(set_attr "type" "fp")])

(define_insn "divsf3"
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
	(div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
		(match_operand:SF 2 "gpc_reg_operand" "f")))]
  ""
  "fd %0,%1,%2"
  [(set_attr "type" "fp")])

(define_insn ""
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
	(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
			  (match_operand:SF 2 "gpc_reg_operand" "f"))
		 (match_operand:SF 3 "gpc_reg_operand" "f")))]
  ""
  "fma %0,%1,%2,%3"
  [(set_attr "type" "fp")])

(define_insn ""
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
	(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
			   (match_operand:SF 2 "gpc_reg_operand" "f"))
		  (match_operand:SF 3 "gpc_reg_operand" "f")))]
  ""
  "fms %0,%1,%2,%3"
  [(set_attr "type" "fp")])

(define_insn ""
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
	(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
				  (match_operand:SF 2 "gpc_reg_operand" "f"))
			 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
  ""
  "fnma %0,%1,%2,%3"
  [(set_attr "type" "fp")])

(define_insn ""
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
	(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
				   (match_operand:SF 2 "gpc_reg_operand" "f"))
			  (match_operand:SF 3 "gpc_reg_operand" "f"))))]
  ""
  "fnms %0,%1,%2,%3"
  [(set_attr "type" "fp")])

(define_insn "negdf2"
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
	(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
  ""
  "fneg %0,%1"
  [(set_attr "type" "fp")])

(define_insn "absdf2"
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
	(abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
  ""
  "fabs %0,%1"
  [(set_attr "type" "fp")])

(define_insn ""
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
	(neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
  ""
  "fnabs %0,%1"
  [(set_attr "type" "fp")])

(define_insn "adddf3"
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
	(plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
		 (match_operand:DF 2 "gpc_reg_operand" "f")))]
  ""
  "fa %0,%1,%2"
  [(set_attr "type" "fp")])

(define_insn "subdf3"
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
	(minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
		  (match_operand:DF 2 "gpc_reg_operand" "f")))]
  ""
  "fs %0,%1,%2"
  [(set_attr "type" "fp")])

(define_insn "muldf3"
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
	(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
		 (match_operand:DF 2 "gpc_reg_operand" "f")))]
  ""
  "fm %0,%1,%2"
  [(set_attr "type" "fp")])

(define_insn "divdf3"
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
	(div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
		(match_operand:DF 2 "gpc_reg_operand" "f")))]
  ""
  "fd %0,%1,%2"
  [(set_attr "type" "fp")])

(define_insn ""
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
	(plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
			  (match_operand:DF 2 "gpc_reg_operand" "f"))
		 (match_operand:DF 3 "gpc_reg_operand" "f")))]
  ""
  "fma %0,%1,%2,%3"
  [(set_attr "type" "fp")])

(define_insn ""
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
	(minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
			   (match_operand:DF 2 "gpc_reg_operand" "f"))
		  (match_operand:DF 3 "gpc_reg_operand" "f")))]
  ""
  "fms %0,%1,%2,%3"
  [(set_attr "type" "fp")])

(define_insn ""
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
	(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
				  (match_operand:DF 2 "gpc_reg_operand" "f"))
			 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
  ""
  "fnma %0,%1,%2,%3"
  [(set_attr "type" "fp")])

(define_insn ""
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
	(neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
				   (match_operand:DF 2 "gpc_reg_operand" "f"))
			  (match_operand:DF 3 "gpc_reg_operand" "f"))))]
  ""
  "fnms %0,%1,%2,%3"
  [(set_attr "type" "fp")])

;; Conversions to and from floating-point.
(define_expand "floatsidf2"
  [(set (match_dup 2)
	(plus:DI (zero_extend:DI
		  (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
			  (match_dup 3)))
		 (match_dup 4)))
   (set (match_operand:DF 0 "gpc_reg_operand" "")
	(minus:DF (subreg:DF (match_dup 2) 0)
		  (match_dup 5)))]
  ""
  "
{
#if HOST_BITS_PER_INT != BITS_PER_WORD
  /* Maybe someone can figure out how to do this in that case.  I don't
     want to right now.  */
  abort ();
#endif

  operands[2] = gen_reg_rtx (DImode);
  operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000);
  operands[4] = immed_double_const (0, 0x43300000, DImode);
  operands[5] = force_reg (DFmode, immed_double_const (0x43300000,
						       0x80000000, DFmode));
}")

(define_expand "floatunssidf2"
  [(set (match_dup 2)
	(plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
		 (match_dup 3)))
   (set (match_operand:DF 0 "gpc_reg_operand" "")
	(minus:DF (subreg:DF (match_dup 2) 0)
		  (match_dup 4)))]
  ""
  "
{
#if HOST_BITS_PER_INT != BITS_PER_WORD
  /* Maybe someone can figure out how to do this in that case.  I don't
     want to right now.  */
  abort ();
#endif

  operands[2] = gen_reg_rtx (DImode);
  operands[3] = immed_double_const (0, 0x43300000, DImode);
  operands[4] = force_reg (DFmode, immed_double_const (0x43300000, 0, DFmode));
}")

;; For the above two cases, we always split.
(define_split
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
	(plus:DI (zero_extend:DI
		  (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
			  (match_operand:SI 2 "logical_operand" "")))
		 (match_operand:DI 3 "immediate_operand" "")))]
  "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
   && GET_CODE (operands[3]) == CONST_DOUBLE
   && CONST_DOUBLE_LOW (operands[3]) == 0"
  [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2)))
   (set (match_dup 4) (match_dup 5))]
  "
{ operands[4] = operand_subword (operands[0], 0, 0, DImode);
  operands[5] = operand_subword (operands[3], 0, 0, DImode);
  operands[6] = operand_subword (operands[0], 1, 0, DImode);
}")

(define_insn ""
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(plus:DI (zero_extend:DI
		  (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
			  (match_operand:SI 2 "logical_operand" "rKJ")))
		 (match_operand:DI 3 "immediate_operand" "n")))]
  "HOST_BITS_PER_INT == BITS_PER_WORD
   && GET_CODE (operands[3]) == CONST_DOUBLE
   && CONST_DOUBLE_LOW (operands[3]) == 0"
  "#")
  
(define_split
  [(set (match_operand:DI 0 "gpc_reg_operand" "=")
	(plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
		 (match_operand:DI 2 "immediate_operand" "")))]
  "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
   && GET_CODE (operands[2]) == CONST_DOUBLE
   && CONST_DOUBLE_LOW (operands[2]) == 0"
  [(set (match_dup 3) (match_dup 4))
   (set (match_dup 5) (match_dup 1))]
  "
{ operands[3] = operand_subword (operands[0], 0, 0, DImode);
  operands[4] = operand_subword (operands[2], 0, 0, DImode);
  operands[5] = operand_subword (operands[0], 1, 0, DImode);

  if (rtx_equal_p (operands[1], operands[5]))
    {
      emit_move_insn (operands[3], operands[4]);
      DONE;
    }

  if (rtx_equal_p (operands[1], operands[3]))
    {
      rtx temp;

      temp = operands[3]; operands[3] = operands[5]; operands[5] = temp;
      temp = operands[4]; operands[4] = operands[1]; operands[1] = temp;
    }
}")

(define_insn ""
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
		 (match_operand:DI 2 "immediate_operand" "n")))]
  "HOST_BITS_PER_INT == BITS_PER_WORD
   && GET_CODE (operands[2]) == CONST_DOUBLE
   && CONST_DOUBLE_LOW (operands[2]) == 0"
  "#")

(define_expand "fix_truncdfsi2"
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
	(fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
  ""
  "
{
  emit_insn (gen_trunc_call (operands[0], operands[1],
			     gen_rtx (SYMBOL_REF, Pmode, \"itrunc\")));
  DONE;
}")

(define_expand "fixuns_truncdfsi2"
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
	(unsigned_fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
  ""
  "
{
  emit_insn (gen_trunc_call (operands[0], operands[1],
			     gen_rtx (SYMBOL_REF, Pmode, \"uitrunc\")));
  DONE;
}")


(define_expand "trunc_call"
  [(parallel [(set (match_operand:SI 0 "" "")
		   (fix:DF (match_operand:DF 1 "" "")))
	      (use (match_operand:SI 2 "" ""))])]
  ""
  "
{
  rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
  rtx first = XVECEXP (insns, 0, 0);
  rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);

  REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
			       REG_NOTES (first));
  REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));

  emit_insn (insns);
  DONE;
}")

(define_expand "trunc_call_rtl"
  [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" ""))
   (use (reg:DF 33))
   (parallel [(set (reg:SI 3)
		   (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
	      (clobber (scratch:SI))])
   (set (match_operand:SI 0 "gpc_reg_operand" "")
	(reg:SI 3))]
  ""
  "
{ 
  rs6000_trunc_used = 1;
}")

;; Define the DImode operations that can be done in a small number
;; of instructions.
(define_insn "adddi3"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
		 (match_operand:DI 2 "gpc_reg_operand" "r")))]
  ""
  "a %L0,%L1,%L2\;ae %0,%1,%2")

(define_insn "subdi3"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
		  (match_operand:DI 2 "gpc_reg_operand" "r")))]
  ""
  "sf %L0,%L2,%L1\;sfe %0,%2,%1")

(define_insn "negdi2"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
  ""
  "sfi %L0,%L1,0\;sfze %0,%1")

(define_insn "mulsidi3"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
   (clobber (match_scratch:SI 3 "=q"))]
  ""
  "mul %0,%1,%2\;mfmq %L0")

;; If operands 0 and 2 are in the same register, we have a problem.  But
;; operands 0 and 1 (the usual case) can be in the same register.  That's
;; why we have the strange constraints below.
(define_insn "ashldi3"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
	(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
		   (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
   (clobber (match_scratch:SI 3 "=X,q,q,q"))]
  ""
  "@
   sli %0,%L1,%h2\;cal %L0,0(0)
   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2")

(define_insn "lshrdi3"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r")
	(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
		     (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
   (clobber (match_scratch:SI 3 "=X,q,q,q"))]
  ""
  "@
   cal %0,0(0)\;s%A2i %L0,%1,%h2
   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
   sr%I2q %0,%1,%h2\;srl%I2q %L0