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A /sys/netccitt/hdlc.h /^#define A 4$/ABM /sys/netccitt/hdlc.h /^#define ABM 3$/ABT_COUNT /sys/net/if_sl.c /^#define ABT_COUNT 3 \/* count of escapes for abort/ABT_ESC /sys/net/if_sl.c /^#define ABT_ESC '\\033' \/* can't be t_intr - dis/ABT_IDLE /sys/net/if_sl.c /^#define ABT_IDLE 1 \/* in seconds - idle before an/ABT_WINDOW /sys/net/if_sl.c /^#define ABT_WINDOW (ABT_COUNT*2+2) \/* in seconds /ACCESSPERMS /sys/sys/stat.h /^#define ACCESSPERMS (S_IRWXU|S_IRWXG|S_IRWXO) \/* /ACKWAIT /sys/netiso/cons_pcb.h /^#define ACKWAIT 0x4$/ACK_DONT /sys/netiso/tp_param.h /^#define ACK_DONT 0$/ACK_DUP /sys/netiso/tp_param.h /^#define ACK_DUP (1<< _ACK_DUP_)$/ACK_EOT /sys/netiso/tp_param.h /^#define ACK_EOT (1<< _ACK_EOT_)$/ACK_REORDER /sys/netiso/tp_param.h /^#define ACK_REORDER (1<< _ACK_REORDER_)$/ACK_STRAT_EACH /sys/netiso/tp_param.h /^#define ACK_STRAT_EACH (1<< _ACK_STRAT_EACH_)$/ACK_STRAT_FULLWIN /sys/netiso/tp_param.h /^#define ACK_STRAT_FULLWIN (1<< _ACK_STRAT_FULLWIN_/ACOMPAT /sys/sys/acct.h /^#define ACOMPAT 0x04 \/* used compatibility mode/ACORE /sys/sys/acct.h /^#define ACORE 0x08 \/* dumped core *\/$/ACT_CONT /sys/sparc/sbus/esp.c /^#define ACT_CONT 0 \/* espact() handled everything/ACT_DONE /sys/sparc/sbus/esp.c /^#define ACT_DONE 2 \/* handled everything, and op /ACT_ERROR /sys/sparc/sbus/esp.c /^#define ACT_ERROR 3 \/* an error occurred, op has /ACT_IO /sys/sparc/sbus/esp.c /^#define ACT_IO 1 \/* espact() is xferring data */ACT_QUICKINTR /sys/sparc/sbus/esp.c /^#define ACT_QUICKINTR 5 \/* another interrupt is e/ACT_RESET /sys/sparc/sbus/esp.c /^#define ACT_RESET 4 \/* please reset ESP, then do /AC_ASYNC_ERR /sys/sparc/include/ctlreg.h /^#define AC_ASYNC_ERR 0x60000008 \/* async error re/AC_ASYNC_VA /sys/sparc/include/ctlreg.h /^#define AC_ASYNC_VA 0x6000000c \/* async error vir/AC_BUS_ERR /sys/sparc/include/ctlreg.h /^#define AC_BUS_ERR 0x60000000 \/* bus error regist/AC_CACHEDATA /sys/sparc/include/ctlreg.h /^#define AC_CACHEDATA 0x90000000 \/* cached data */AC_CACHETAGS /sys/sparc/include/ctlreg.h /^#define AC_CACHETAGS 0x80000000 \/* cache tag base/AC_CONTEXT /sys/sparc/include/ctlreg.h /^#define AC_CONTEXT 0x30000000 \/* context register/AC_DIAG_REG /sys/sparc/include/ctlreg.h /^#define AC_DIAG_REG 0x70000000 \/* diagnostic reg /AC_DVMA_ENABLE /sys/sparc/include/ctlreg.h /^#define AC_DVMA_ENABLE 0x50000000 \/* enable user /AC_DVMA_MAP /sys/sparc/include/ctlreg.h /^#define AC_DVMA_MAP 0xd0000000 \/* user dvma map e/AC_SERIAL /sys/sparc/include/ctlreg.h /^#define AC_SERIAL 0xf0000000 \/* special serial po/AC_SYNC_ERR /sys/sparc/include/ctlreg.h /^#define AC_SYNC_ERR 0x60000000 \/* sync (memory) e/AC_SYNC_VA /sys/sparc/include/ctlreg.h /^#define AC_SYNC_VA 0x60000004 \/* sync error virtu/AC_SYSENABLE /sys/sparc/include/ctlreg.h /^#define AC_SYSENABLE 0x40000000 \/* system enable /ADD /sys/sparc/fpu/fpu_mul.c /^#define ADD \/* A += X *\/ \\$/ADDCARRY /sys/netinet/in_cksum.c /^#define ADDCARRY(x) (x > 65535 ? x -= 65535 : x)$/ADDDOMAIN /sys/kern/uipc_domain.c /^#define ADDDOMAIN(x) { \\$/ADDOPTION /sys/netiso/tp_param.h /^#define ADDOPTION(type, DU, len, src)\\$/ADDRESS_A /sys/netccitt/hdlc.h /^#define ADDRESS_A 3 \/* B'00000011' *\/$/ADDRESS_B /sys/netccitt/hdlc.h /^#define ADDRESS_B 1 \/* B'00000001' *\/$/ADDRLN /sys/netccitt/pk.h /^#define ADDRLN 1$/ADDR_DESTUNKNOWN /sys/netiso/clnp.h /^#define ADDR_DESTUNKNOWN 0x81 \/* destination addr/ADDR_DESTUNREACH /sys/netiso/clnp.h /^#define ADDR_DESTUNREACH 0x80 \/* destination addr/ADDUPROF /sys/sys/resourcevar.h /^#define ADDUPROF(p) \\$/ADVANCE /sys/net/rtsock.c /^#define ADVANCE(x, n) (x += ROUNDUP((n)->sa_len))$/AER_BITS /sys/sparc/include/ctlreg.h /^#define AER_BITS "\\20\\10WBINVAL\\6TIMEOUT\\5DVMA/AER_DVMAERR /sys/sparc/include/ctlreg.h /^#define AER_DVMAERR 0x10 \/* bus error during DVM/AER_TIMEOUT /sys/sparc/include/ctlreg.h /^#define AER_TIMEOUT 0x20 \/* bus timeout *\/$/AER_WBINVAL /sys/sparc/include/ctlreg.h /^#define AER_WBINVAL 0x80 \/* writeback found PTE /AFI_37 /sys/netiso/iso.h /^#define AFI_37 0x37 \/* bcd of "37" *\/$/AFI_OSINET /sys/netiso/iso.h /^#define AFI_OSINET 0x47 \/* bcd of "47" *\/$/AFI_RFC986 /sys/netiso/iso.h /^#define AFI_RFC986 0x47 \/* bcd of "47" *\/$/AFI_SNA /sys/netiso/iso.h /^#define AFI_SNA 0x00 \/* SubNetwork Address; inva/AFORK /sys/sys/acct.h /^#define AFORK 0x01 \/* forked but not execed *\//AFS_VFSOPS /sys/kern/vfs_conf.c /^#define AFS_VFSOPS &afs_vfsops$/AF_APPLETALK /sys/sys/socket.h /^#define AF_APPLETALK 16 \/* Apple Talk *\/$/AF_CCITT /sys/sys/socket.h /^#define AF_CCITT 10 \/* CCITT protocols, X.25 etc/AF_CHAOS /sys/sys/socket.h /^#define AF_CHAOS 5 \/* mit CHAOS protocols *\/$/AF_CNT /sys/sys/socket.h /^#define AF_CNT 21 \/* Computer Network Technolog/AF_COIP /sys/sys/socket.h /^#define AF_COIP 20 \/* connection-oriented IP, a/AF_DATAKIT /sys/sys/socket.h /^#define AF_DATAKIT 9 \/* datakit protocols *\/$/AF_DECnet /sys/sys/socket.h /^#define AF_DECnet 12 \/* DECnet *\/$/AF_DLI /sys/sys/socket.h /^#define AF_DLI 13 \/* DEC Direct data link inter/AF_ECMA /sys/sys/socket.h /^#define AF_ECMA 8 \/* european computer manufact/AF_HYLINK /sys/sys/socket.h /^#define AF_HYLINK 15 \/* NSC Hyperchannel *\/$/AF_IMPLINK /sys/sys/socket.h /^#define AF_IMPLINK 3 \/* arpanet imp addresses */AF_INET /sys/sys/socket.h /^#define AF_INET 2 \/* internetwork: UDP, TCP, et/AF_IPX /sys/sys/socket.h /^#define AF_IPX 23 \/* Novell Internet Protocol */AF_ISO /sys/sys/socket.h /^#define AF_ISO 7 \/* ISO protocols *\/$/AF_LAT /sys/sys/socket.h /^#define AF_LAT 14 \/* LAT *\/$/AF_LINK /sys/sys/socket.h /^#define AF_LINK 18 \/* Link layer interface *\/$/AF_LOCAL /sys/sys/socket.h /^#define AF_LOCAL 1 \/* local to host (pipes, port/AF_MAX /sys/sys/socket.h /^#define AF_MAX 26$/AF_NS /sys/sys/socket.h /^#define AF_NS 6 \/* XEROX NS protocols *\/$/AF_OSI /sys/sys/socket.h /^#define AF_OSI AF_ISO$/AF_PUP /sys/sys/socket.h /^#define AF_PUP 4 \/* pup protocols: e.g. BSP *\//AF_ROUTE /sys/sys/socket.h /^#define AF_ROUTE 17 \/* Internal Routing Protocol/AF_SIP /sys/sys/socket.h /^#define AF_SIP 24 \/* Simple Internet Protocol */AF_SNA /sys/sys/socket.h /^#define AF_SNA 11 \/* IBM SNA *\/$/AF_UNIX /sys/sys/socket.h /^#define AF_UNIX AF_LOCAL \/* backward compatibili/AF_UNSPEC /sys/sys/socket.h /^#define AF_UNSPEC 0 \/* unspecified *\/$/AHZ /sys/sys/acct.h /^#define AHZ 64$/AK_TPDU /sys/netiso/tp_events.h /^#define AK_TPDU 0xb$/AK_TPDU_type /sys/netiso/tp_param.h /^#define AK_TPDU_type 0x6$/ALIGN /sys/sparc/include/param.h /^#define ALIGN(p) (((u_int)(p) + ALIGNBYTES) & ~ALI/ALIGNBYTES /sys/sparc/include/param.h /^#define ALIGNBYTES 7$/ALLDELAY /sys/sys/ioctl_compat.h /^#define ALLDELAY (NLDELAY|TBDELAY|CRDELAY|VTDELAY/ALLPERMS /sys/sys/stat.h /^#define ALLPERMS (S_ISUID|S_ISGID|S_ISTXT|S_IRWXU|/ALPHA /sys/kern/tty.c /^#define ALPHA 0x40 \/* Alpha or underscore. *\/$/ALTWERASE /sys/sys/termios.h /^#define ALTWERASE 0x00000200 \/* use alternate WER/AMDR_DLC_12_15 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_12_15 0x90$/AMDR_DLC_1_7 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_1_7 0x88$/AMDR_DLC_ASR /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_ASR 0x91$/AMDR_DLC_DMR1 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_DMR1 0x86$/AMDR_DLC_DMR2 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_DMR2 0x87$/AMDR_DLC_DMR3 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_DMR3 0x8e$/AMDR_DLC_DMR4 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_DMR4 0x8f$/AMDR_DLC_DRCR /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_DRCR 0x89$/AMDR_DLC_DRLR /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_DRLR 0x84$/AMDR_DLC_DTCR /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_DTCR 0x85$/AMDR_DLC_FRAR123 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_FRAR123 0x81$/AMDR_DLC_FRAR4 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_FRAR4 0x8c$/AMDR_DLC_RNGR1 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_RNGR1 0x8a$/AMDR_DLC_RNGR2 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_RNGR2 0x8b$/AMDR_DLC_SRAR123 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_SRAR123 0x82$/AMDR_DLC_SRAR4 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_SRAR4 0x8d$/AMDR_DLC_TAR /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_DLC_TAR 0x83$/AMDR_INIT /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_INIT 0x21$/AMDR_LIU_2_4 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_LIU_2_4 0xa5$/AMDR_LIU_LMR1 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_LIU_LMR1 0xa3$/AMDR_LIU_LMR2 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_LIU_LMR2 0xa4$/AMDR_LIU_LPR /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_LIU_LPR 0xa2$/AMDR_LIU_LSR /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_LIU_LSR 0xa1$/AMDR_LIU_MF /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_LIU_MF 0xa6$/AMDR_LIU_MFQB /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_LIU_MFQB 0xa8$/AMDR_LIU_MFSB /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_LIU_MFSB 0xa7$/AMDR_MAP_1_10 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_MAP_1_10 0x6b$/AMDR_MAP_ATGR /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_MAP_ATGR 0x68$/AMDR_MAP_FTGR /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_MAP_FTGR 0x67$/AMDR_MAP_GER /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_MAP_GER 0x65$/AMDR_MAP_GR /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_MAP_GR 0x64$/AMDR_MAP_GX /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_MAP_GX 0x63$/AMDR_MAP_MMR1 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_MAP_MMR1 0x69$/AMDR_MAP_MMR2 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_MAP_MMR2 0x6a$/AMDR_MAP_R /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_MAP_R 0x62$/AMDR_MAP_STG /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_MAP_STG 0x66$/AMDR_MAP_X /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_MAP_X 0x61$/AMDR_MUX_1_4 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_MUX_1_4 0x45$/AMDR_MUX_MCR1 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_MUX_MCR1 0x41$/AMDR_MUX_MCR2 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_MUX_MCR2 0x42$/AMDR_MUX_MCR3 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_MUX_MCR3 0x43$/AMDR_MUX_MCR4 /sys/sparc/dev/bsd_audioreg.h /^#define AMDR_MUX_MCR4 0x44$/AMD_INIT_AS_RX /sys/sparc/dev/bsd_audioreg.h /^#define AMD_INIT_AS_RX (0x01 << 6)$/AMD_INIT_AS_TX /sys/sparc/dev/bsd_audioreg.h /^#define AMD_INIT_AS_TX (0x01 << 7)$/AMD_INIT_CDS_DIV1 /sys/sparc/dev/bsd_audioreg.h /^#define AMD_INIT_CDS_DIV1 (0x01 << 3)$/AMD_INIT_CDS_DIV2 /sys/sparc/dev/bsd_audioreg.h /^#define AMD_INIT_CDS_DIV2 (0x00 << 3)$/AMD_INIT_CDS_DIV4 /sys/sparc/dev/bsd_audioreg.h /^#define AMD_INIT_CDS_DIV4 (0x02 << 3)$/AMD_INIT_INT_DISABLE /sys/sparc/dev/bsd_audioreg.h /^#define AMD_INIT_INT_DISABLE (0x01 << 2)$/AMD_INIT_PMS_ACTIVE /sys/sparc/dev/bsd_audioreg.h /^#define AMD_INIT_PMS_ACTIVE 0x01$/AMD_INIT_PMS_ACTIVE_DATA /sys/sparc/dev/bsd_audioreg.h /^#define AMD_INIT_PMS_ACTIVE_DATA 0x02$/AMD_INIT_PMS_IDLE /sys/sparc/dev/bsd_audioreg.h /^#define AMD_INIT_PMS_IDLE 0x00$/AMD_MCR4_INT_ENABLE /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MCR4_INT_ENABLE (1 << 3)$/AMD_MCR4_SWAPBB /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MCR4_SWAPBB (1 << 4)$/AMD_MCR4_SWAPBC /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MCR4_SWAPBC (1 << 5)$/AMD_MCRCHAN_B1 /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MCRCHAN_B1 0x01$/AMD_MCRCHAN_B2 /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MCRCHAN_B2 0x02$/AMD_MCRCHAN_BA /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MCRCHAN_BA 0x03$/AMD_MCRCHAN_BB /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MCRCHAN_BB 0x04$/AMD_MCRCHAN_BC /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MCRCHAN_BC 0x05$/AMD_MCRCHAN_BD /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MCRCHAN_BD 0x06$/AMD_MCRCHAN_BE /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MCRCHAN_BE 0x07$/AMD_MCRCHAN_BF /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MCRCHAN_BF 0x08$/AMD_MCRCHAN_NC /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MCRCHAN_NC 0x00$/AMD_MMR1_ALAW /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MMR1_ALAW 0x01$/AMD_MMR1_GER /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MMR1_GER 0x08$/AMD_MMR1_GR /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MMR1_GR 0x04$/AMD_MMR1_GX /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MMR1_GX 0x02$/AMD_MMR1_LOOP /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MMR1_LOOP 0x80$/AMD_MMR1_R /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MMR1_R 0x20$/AMD_MMR1_STG /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MMR1_STG 0x40$/AMD_MMR1_X /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MMR1_X 0x10$/AMD_MMR2_AINB /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MMR2_AINB 0x01$/AMD_MMR2_DIS_AZ /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MMR2_DIS_AZ 0x40$/AMD_MMR2_DIS_HPF /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MMR2_DIS_HPF 0x20$/AMD_MMR2_DTMF /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MMR2_DTMF 0x04$/AMD_MMR2_GEN /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MMR2_GEN 0x08$/AMD_MMR2_LS /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MMR2_LS 0x02$/AMD_MMR2_RNG /sys/sparc/dev/bsd_audioreg.h /^#define AMD_MMR2_RNG 0x10$/ANY /sys/sparc/sparc/cpu.c /^#define ANY 0xff \/* match any FPU version (or, la/ANYP /sys/sys/ioctl_compat.h /^#define ANYP 0x000000c0 \/* get any parity\/send/APPEND /sys/sys/stat.h /^#define APPEND (UF_APPEND | SF_APPEND)$/ARCDENSITY /sys/sys/gmon.h /^#define ARCDENSITY 2$/ARGMAPSIZE /sys/sys/map.h /^#define ARGMAPSIZE 16$/ARGO_DEBUG /sys/netiso/argo_debug.h /^#define ARGO_DEBUG$/ARGS /sys/sparc/rcons/raster.h /^#define ARGS(alist) alist$/
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