zsreg.h

早期freebsd实现

/*
 * Copyright (c) 1992, 1993
 *	The Regents of the University of California.  All rights reserved.
 *
 * This software was developed by the Computer Systems Engineering group
 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
 * contributed to Berkeley.
 *
 * All advertising materials mentioning features or use of this software
 * must display the following acknowledgement:
 *	This product includes software developed by the University of
 *	California, Lawrence Berkeley Laboratory.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by the University of
 *	California, Berkeley and its contributors.
 * 4. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	@(#)zsreg.h	8.1 (Berkeley) 6/11/93
 *
 * from: $Header: zsreg.h,v 1.7 92/11/26 01:27:18 torek Exp $ (LBL)
 */

/*
 * Zilog SCC registers, as implemented on the Sun-4c.
 *
 * Each Z8530 implements two channels (called `a' and `b').
 *
 * The damnable chip was designed to fit on Z80 I/O ports, and thus
 * has everything multiplexed out the wazoo.  We have to select
 * a register, then read or write the register, and so on.  Worse,
 * the parameter bits are scattered all over the register space.
 * This thing is full of `miscellaneous' control registers.
 *
 * Worse yet, the registers have incompatible functions on read
 * and write operations.  We describe the registers below according
 * to whether they are `read registers' (RR) or `write registers' (WR).
 * As if this were not enough, some of the channel B status bits show
 * up in channel A, and vice versa.  The blasted thing shares write
 * registers 2 and 9 across both channels, and reads registers 2 and 3
 * differently for the two channels.  We can, however, ignore this much
 * of the time.
 */
#ifndef LOCORE
struct zschan {
	u_char	zc_csr;		/* control and status, and indirect access */
	u_char	zc_xxx0;
	u_char	zc_data;	/* data */
	u_char	zc_xxx1;
};

/*
 * N.B.: the keyboard is channel 1, the mouse channel 0; ttyb is 1, ttya
 * is 0.  In other words, the things are BACKWARDS.
 */
struct zsdevice {
	struct	zschan zs_chan[2];	/* channel A = 1, B = 0 */
};

#define	CHAN_A	1
#define	CHAN_B	0
#endif

/*
 * Some of the names in this files were chosen to make the hsis driver
 * work unchanged (which means that they will match some in SunOS).
 *
 * `S.C.' stands for Special Condition, which is any of these:
 *	receiver overrun	(aka silo overflow)
 *	framing error		(missing stop bit, etc)
 *	end of frame		(in synchronous modes)
 *	parity error		(when `parity error is S.C.' is set)
 */

/*
 * Registers with only a single `numeric value' get a name.
 * Other registers hold bits and are only numbered; the bit
 * definitions imply the register number (see below).
 *
 * We never use the receive and transmit data registers as
 * indirects (choosing instead the zc_data register), so they
 * are not defined here.
 */
#define	ZSRR_IVEC	2	/* interrupt vector (channel 0) */
#define	ZSRR_IPEND	3	/* interrupt pending (ch. 0 only) */
#define	ZSRR_BAUDLO	12	/* baud rate generator (low half) */
#define	ZSRR_BAUDHI	13	/* baud rate generator (high half) */

#define	ZSWR_IVEC	2	/* interrupt vector (shared) */
#define	ZSWR_TXSYNC	6	/* sync transmit char (monosync mode) */
#define	ZSWR_RXSYNC	7	/* sync receive char (monosync mode) */
#define	ZSWR_SYNCLO	6	/* sync low byte (bisync mode) */
#define	ZSWR_SYNCHI	7	/* sync high byte (bisync mode) */
#define	ZSWR_SDLC_ADDR	6	/* SDLC address (SDLC mode) */
#define	ZSWR_SDLC_FLAG	7	/* SDLC flag 0x7E (SDLC mode) */
#define	ZSWR_BAUDLO	12	/* baud rate generator (low half) */
#define	ZSWR_BAUDHI	13	/* baud rate generator (high half) */

/*
 * Registers 0 through 7 may be written with any one of the 8 command
 * modifiers, and/or any one of the 4 reset modifiers, defined below.
 * To write registers 8 through 15, however, the command modifier must
 * always be `point high'.  Rather than track this bizzareness all over
 * the driver, we try to avoid using any modifiers, ever (but they are
 * defined here if you want them).
 */
#define	ZSM_RESET_TXUEOM	0xc0	/* reset xmit underrun / eom latch */
#define	ZSM_RESET_TXCRC		0x80	/* reset xmit crc generator */
#define	ZSM_RESET_RXCRC		0x40	/* reset recv crc checker */
#define	ZSM_NULL		0x00	/* nothing special */

#define	ZSM_RESET_IUS		0x38	/* reset interrupt under service */
#define	ZSM_RESET_ERR		0x30	/* reset error cond */
#define	ZSM_RESET_TXINT		0x28	/* reset xmit interrupt pending */
#define	ZSM_EI_NEXTRXC		0x20	/* enable int. on next rcvd char */
#define	ZSM_SEND_ABORT		0x18	/* send abort (SDLC) */
#define	ZSM_RESET_STINT		0x10	/* reset external/status interrupt */
#define	ZSM_POINTHIGH		0x08	/* `point high' (use r8-r15) */
#define	ZSM_NULL		0x00	/* nothing special */

/*
 * Commands for Write Register 0 (`Command Register').
 * These are just the command modifiers or'ed with register number 0
 * (which of course equals the command modifier).
 */
#define	ZSWR0_RESET_EOM		ZSM_RESET_TXUEOM
#define	ZSWR0_RESET_TXCRC	ZSM_RESET_TXCRC
#define	ZSWR0_RESET_RXCRC	ZSM_RESET_RXCRC
#define	ZSWR0_CLR_INTR		ZSM_RESET_IUS
#define	ZSWR0_RESET_ERRORS	ZSM_RESET_ERR
#define	ZSWR0_EI_NEXTRXC	ZSM_EI_NEXTRXC
#define	ZSWR0_SEND_ABORT	ZSM_SEND_ABORT
#define	ZSWR0_RESET_STATUS	ZSM_RESET_STINT
#define	ZSWR0_RESET_TXINT	ZSM_RESET_TXINT

/*
 * Bits in Write Register 1 (`Transmit/Receive Interrupt and Data
 * Transfer Mode Definition').  Note that bits 3 and 4 are taken together
 * as a single unit, and bits 5 and 6 are useful only if bit 7 is set.
 */
#define	ZSWR1_REQ_WAIT		0x80	/* WAIT*-REQ* pin gives WAIT* */
#define	ZSWR1_REQ_REQ		0xc0	/* WAIT*-REQ* pin gives REQ* */
#define	ZSWR1_REQ_TX		0x00	/* WAIT*-REQ* pin follows xmit buf */
#define	ZSWR1_REQ_RX		0x20	/* WAIT*-REQ* pin follows recv buf */

#define	ZSWR1_RIE_NONE		0x00	/* disable rxint entirely */
#define	ZSWR1_RIE_FIRST		0x08	/* rxint on first char & on S.C. */
#define	ZSWR1_RIE		0x10	/* rxint per char & on S.C. */
#define	ZSWR1_RIE_SPECIAL_ONLY	0x18	/* rxint on S.C. only */

#define	ZSWR1_PE_SC		0x04	/* parity error is special condition */
#define	ZSWR1_TIE		0x02	/* transmit interrupt enable */
#define	ZSWR1_SIE		0x01	/* external/status interrupt enable */

/* HSIS compat */
#define	ZSWR1_REQ_ENABLE	(ZSWR1_REQ_WAIT | ZSWR1_REQ_TX)

/*
 * Bits in Write Register 3 (`Receive Parameters and Control').
 * Bits 7 and 6 are taken as a unit.  Note that the receive bits
 * per character ordering is insane.
 *
 * Here `hardware flow control' means CTS enables the transmitter
 * and DCD enables the receiver.  The latter is neither interesting
 * nor useful, and gets in our way, making it almost unusable.
 */
#define	ZSWR3_RX_5		0x00	/* receive 5 bits per char */
#define	ZSWR3_RX_7		0x40	/* receive 7 bits per char */
#define	ZSWR3_RX_6		0x80	/* receive 6 bits per char */
#define	ZSWR3_RX_8		0xc0	/* receive 8 bits per char */

#define	ZSWR3_HFC		0x20	/* hardware flow control */
#define	ZSWR3_HUNT		0x10	/* enter hunt mode */
#define	ZSWR3_RXCRC_ENABLE	0x08	/* enable recv crc calculation */
#define	ZSWR3_ADDR_SEARCH_MODE	0x04	/* address search mode (SDLC only) */
#define	ZSWR3_SYNC_LOAD_INH	0x02	/* sync character load inhibit */
#define	ZSWR3_RX_ENABLE		0x01	/* receiver enable */

/*
 * Bits in Write Register 4 (`Transmit/Receive Miscellaneous Parameters
 * and Modes').  Bits 7&6, 5&4, and 3&2 are taken as units.
 */
#define	ZSWR4_CLK_X1		0x00	/* clock divisor = 1 */
#define	ZSWR4_CLK_X16		0x40	/* clock divisor = 16 */
#define	ZSWR4_CLK_X32		0x80	/* clock divisor = 32 */
#define	ZSWR4_CLK_X64		0xc0	/* clock divisor = 64 */

#define	ZSWR4_MONOSYNC		0x00	/* 8 bit sync char (sync only) */
#define	ZSWR4_BISYNC		0x10	/* 16 bit sync char (sync only) */
#define	ZSWR4_SDLC		0x20	/* SDLC mode */
#define	ZSWR4_EXTSYNC		0x30	/* external sync mode */

#define	ZSWR4_SYNCMODE		0x00	/* one of the above sync modes */
#define	ZSWR4_ONESB		0x04	/* 1 stop bit */