📄 fp.s
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result_fs_w: jal set_fd_word # save result (in t2) b doneresult_ft_d: move t0, t4 # result is FT move t1, t5 move t2, t6 move t3, t7result_fs_d: # result is FS jal set_fd_d # save result (in t0,t1,t2,t3)done: lw ra, STAND_RA_OFFSET(sp) addu sp, sp, STAND_FRAME_SIZE j raEND(MachEmulateFP)/*---------------------------------------------------------------------------- * get_fs_int -- * * Read (integer) the FS register (bits 15-11). * This is an internal routine used by MachEmulateFP only. * * Results: * t0 contains the sign * t2 contains the fraction * *---------------------------------------------------------------------------- */LEAF(get_fs_int) srl a3, a0, 12 - 2 # get FS field (even regs only) and a3, a3, 0xF << 2 # mask FS field lw a3, get_fs_int_tbl(a3) # switch on register number j a3 .rdataget_fs_int_tbl: .word get_fs_int_f0 .word get_fs_int_f2 .word get_fs_int_f4 .word get_fs_int_f6 .word get_fs_int_f8 .word get_fs_int_f10 .word get_fs_int_f12 .word get_fs_int_f14 .word get_fs_int_f16 .word get_fs_int_f18 .word get_fs_int_f20 .word get_fs_int_f22 .word get_fs_int_f24 .word get_fs_int_f26 .word get_fs_int_f28 .word get_fs_int_f30 .textget_fs_int_f0: mfc1 t2, $f0 b get_fs_int_doneget_fs_int_f2: mfc1 t2, $f2 b get_fs_int_doneget_fs_int_f4: mfc1 t2, $f4 b get_fs_int_doneget_fs_int_f6: mfc1 t2, $f6 b get_fs_int_doneget_fs_int_f8: mfc1 t2, $f8 b get_fs_int_doneget_fs_int_f10: mfc1 t2, $f10 b get_fs_int_doneget_fs_int_f12: mfc1 t2, $f12 b get_fs_int_doneget_fs_int_f14: mfc1 t2, $f14 b get_fs_int_doneget_fs_int_f16: mfc1 t2, $f16 b get_fs_int_doneget_fs_int_f18: mfc1 t2, $f18 b get_fs_int_doneget_fs_int_f20: mfc1 t2, $f20 b get_fs_int_doneget_fs_int_f22: mfc1 t2, $f22 b get_fs_int_doneget_fs_int_f24: mfc1 t2, $f24 b get_fs_int_doneget_fs_int_f26: mfc1 t2, $f26 b get_fs_int_doneget_fs_int_f28: mfc1 t2, $f28 b get_fs_int_doneget_fs_int_f30: mfc1 t2, $f30get_fs_int_done: srl t0, t2, 31 # init the sign bit bge t2, zero, 1f negu t21: j raEND(get_fs_int)/*---------------------------------------------------------------------------- * get_ft_fs_s -- * * Read (single precision) the FT register (bits 20-16) and * the FS register (bits 15-11) and break up into fields. * This is an internal routine used by MachEmulateFP only. * * Results: * t0 contains the FS sign * t1 contains the FS (biased) exponent * t2 contains the FS fraction * t4 contains the FT sign * t5 contains the FT (biased) exponent * t6 contains the FT fraction * *---------------------------------------------------------------------------- */LEAF(get_ft_fs_s) srl a3, a0, 17 - 2 # get FT field (even regs only) and a3, a3, 0xF << 2 # mask FT field lw a3, get_ft_s_tbl(a3) # switch on register number j a3 .rdataget_ft_s_tbl: .word get_ft_s_f0 .word get_ft_s_f2 .word get_ft_s_f4 .word get_ft_s_f6 .word get_ft_s_f8 .word get_ft_s_f10 .word get_ft_s_f12 .word get_ft_s_f14 .word get_ft_s_f16 .word get_ft_s_f18 .word get_ft_s_f20 .word get_ft_s_f22 .word get_ft_s_f24 .word get_ft_s_f26 .word get_ft_s_f28 .word get_ft_s_f30 .textget_ft_s_f0: mfc1 t4, $f0 b get_ft_s_doneget_ft_s_f2: mfc1 t4, $f2 b get_ft_s_doneget_ft_s_f4: mfc1 t4, $f4 b get_ft_s_doneget_ft_s_f6: mfc1 t4, $f6 b get_ft_s_doneget_ft_s_f8: mfc1 t4, $f8 b get_ft_s_doneget_ft_s_f10: mfc1 t4, $f10 b get_ft_s_doneget_ft_s_f12: mfc1 t4, $f12 b get_ft_s_doneget_ft_s_f14: mfc1 t4, $f14 b get_ft_s_doneget_ft_s_f16: mfc1 t4, $f16 b get_ft_s_doneget_ft_s_f18: mfc1 t4, $f18 b get_ft_s_doneget_ft_s_f20: mfc1 t4, $f20 b get_ft_s_doneget_ft_s_f22: mfc1 t4, $f22 b get_ft_s_doneget_ft_s_f24: mfc1 t4, $f24 b get_ft_s_doneget_ft_s_f26: mfc1 t4, $f26 b get_ft_s_doneget_ft_s_f28: mfc1 t4, $f28 b get_ft_s_doneget_ft_s_f30: mfc1 t4, $f30get_ft_s_done: srl t5, t4, 23 # get exponent and t5, t5, 0xFF and t6, t4, 0x7FFFFF # get fraction srl t4, t4, 31 # get sign bne t5, SEXP_INF, 1f # is it a signaling NAN? and v0, t6, SSIGNAL_NAN bne v0, zero, invalid_s1: /* fall through to get FS *//*---------------------------------------------------------------------------- * get_fs_s -- * * Read (single precision) the FS register (bits 15-11) and * break up into fields. * This is an internal routine used by MachEmulateFP only. * * Results: * t0 contains the sign * t1 contains the (biased) exponent * t2 contains the fraction * *---------------------------------------------------------------------------- */ALEAF(get_fs_s) srl a3, a0, 12 - 2 # get FS field (even regs only) and a3, a3, 0xF << 2 # mask FS field lw a3, get_fs_s_tbl(a3) # switch on register number j a3 .rdataget_fs_s_tbl: .word get_fs_s_f0 .word get_fs_s_f2 .word get_fs_s_f4 .word get_fs_s_f6 .word get_fs_s_f8 .word get_fs_s_f10 .word get_fs_s_f12 .word get_fs_s_f14 .word get_fs_s_f16 .word get_fs_s_f18 .word get_fs_s_f20 .word get_fs_s_f22 .word get_fs_s_f24 .word get_fs_s_f26 .word get_fs_s_f28 .word get_fs_s_f30 .textget_fs_s_f0: mfc1 t0, $f0 b get_fs_s_doneget_fs_s_f2: mfc1 t0, $f2 b get_fs_s_doneget_fs_s_f4: mfc1 t0, $f4 b get_fs_s_doneget_fs_s_f6: mfc1 t0, $f6 b get_fs_s_doneget_fs_s_f8: mfc1 t0, $f8 b get_fs_s_doneget_fs_s_f10: mfc1 t0, $f10 b get_fs_s_doneget_fs_s_f12: mfc1 t0, $f12 b get_fs_s_doneget_fs_s_f14: mfc1 t0, $f14 b get_fs_s_doneget_fs_s_f16: mfc1 t0, $f16 b get_fs_s_doneget_fs_s_f18: mfc1 t0, $f18 b get_fs_s_doneget_fs_s_f20: mfc1 t0, $f20 b get_fs_s_doneget_fs_s_f22: mfc1 t0, $f22 b get_fs_s_doneget_fs_s_f24: mfc1 t0, $f24 b get_fs_s_doneget_fs_s_f26: mfc1 t0, $f26 b get_fs_s_doneget_fs_s_f28: mfc1 t0, $f28 b get_fs_s_doneget_fs_s_f30: mfc1 t0, $f30get_fs_s_done: srl t1, t0, 23 # get exponent and t1, t1, 0xFF and t2, t0, 0x7FFFFF # get fraction srl t0, t0, 31 # get sign bne t1, SEXP_INF, 1f # is it a signaling NAN? and v0, t2, SSIGNAL_NAN bne v0, zero, invalid_s1: j raEND(get_ft_fs_s)/*---------------------------------------------------------------------------- * get_ft_fs_d -- * * Read (double precision) the FT register (bits 20-16) and * the FS register (bits 15-11) and break up into fields. * This is an internal routine used by MachEmulateFP only. * * Results: * t0 contains the FS sign * t1 contains the FS (biased) exponent * t2 contains the FS fraction * t3 contains the FS remaining fraction * t4 contains the FT sign * t5 contains the FT (biased) exponent * t6 contains the FT fraction * t7 contains the FT remaining fraction * *---------------------------------------------------------------------------- */LEAF(get_ft_fs_d) srl a3, a0, 17 - 2 # get FT field (even regs only) and a3, a3, 0xF << 2 # mask FT field lw a3, get_ft_d_tbl(a3) # switch on register number j a3 .rdataget_ft_d_tbl: .word get_ft_d_f0 .word get_ft_d_f2 .word get_ft_d_f4 .word get_ft_d_f6 .word get_ft_d_f8 .word get_ft_d_f10 .word get_ft_d_f12 .word get_ft_d_f14 .word get_ft_d_f16 .word get_ft_d_f18 .word get_ft_d_f20 .word get_ft_d_f22 .word get_ft_d_f24 .word get_ft_d_f26 .word get_ft_d_f28 .word get_ft_d_f30 .textget_ft_d_f0: mfc1 t7, $f0 mfc1 t4, $f1 b get_ft_d_doneget_ft_d_f2: mfc1 t7, $f2 mfc1 t4, $f3 b get_ft_d_doneget_ft_d_f4: mfc1 t7, $f4 mfc1 t4, $f5 b get_ft_d_doneget_ft_d_f6: mfc1 t7, $f6 mfc1 t4, $f7 b get_ft_d_doneget_ft_d_f8: mfc1 t7, $f8 mfc1 t4, $f9 b get_ft_d_doneget_ft_d_f10: mfc1 t7, $f10 mfc1 t4, $f11 b get_ft_d_doneget_ft_d_f12: mfc1 t7, $f12 mfc1 t4, $f13 b get_ft_d_doneget_ft_d_f14: mfc1 t7, $f14 mfc1 t4, $f15 b get_ft_d_doneget_ft_d_f16: mfc1 t7, $f16 mfc1 t4, $f17 b get_ft_d_doneget_ft_d_f18: mfc1 t7, $f18 mfc1 t4, $f19 b get_ft_d_doneget_ft_d_f20: mfc1 t7, $f20 mfc1 t4, $f21 b get_ft_d_doneget_ft_d_f22: mfc1 t7, $f22 mfc1 t4, $f23 b get_ft_d_doneget_ft_d_f24: mfc1 t7, $f24 mfc1 t4, $f25 b get_ft_d_doneget_ft_d_f26: mfc1 t7, $f26 mfc1 t4, $f27 b get_ft_d_doneget_ft_d_f28: mfc1 t7, $f28 mfc1 t4, $f29 b get_ft_d_doneget_ft_d_f30: mfc1 t7, $f30 mfc1 t4, $f31get_ft_d_done: srl t5, t4, 20 # get exponent and t5, t5, 0x7FF and t6, t4, 0xFFFFF # get fraction srl t4, t4, 31 # get sign bne t5, DEXP_INF, 1f # is it a signaling NAN? and v0, t6, DSIGNAL_NAN bne v0, zero, invalid_d1: /* fall through to get FS *//*---------------------------------------------------------------------------- * get_fs_d -- * * Read (double precision) the FS register (bits 15-11) and * break up into fields. * This is an internal routine used by MachEmulateFP only. * * Results: * t0 contains the sign * t1 contains the (biased) exponent * t2 contains the fraction * t3 contains the remaining fraction * *---------------------------------------------------------------------------- */ALEAF(get_fs_d) srl a3, a0, 12 - 2 # get FS field (even regs only) and a3, a3, 0xF << 2 # mask FS field lw a3, get_fs_d_tbl(a3) # switch on register number j a3 .rdataget_fs_d_tbl: .word get_fs_d_f0 .word get_fs_d_f2 .word get_fs_d_f4 .word get_fs_d_f6 .word get_fs_d_f8 .word get_fs_d_f10 .word get_fs_d_f12 .word get_fs_d_f14 .word get_fs_d_f16 .word get_fs_d_f18 .word get_fs_d_f20 .word get_fs_d_f22 .word get_fs_d_f24 .word get_fs_d_f26 .word get_fs_d_f28 .word get_fs_d_f30 .textget_fs_d_f0: mfc1 t3, $f0 mfc1 t0, $f1 b get_fs_d_doneget_fs_d_f2: mfc1 t3, $f2 mfc1 t0, $f3 b get_fs_d_doneget_fs_d_f4: mfc1 t3, $f4 mfc1 t0, $f5 b get_fs_d_doneget_fs_d_f6: mfc1 t3, $f6 mfc1 t0, $f7 b get_fs_d_doneget_fs_d_f8: mfc1 t3, $f8 mfc1 t0, $f9 b get_fs_d_doneget_fs_d_f10: mfc1 t3, $f10 mfc1 t0, $f11 b get_fs_d_doneget_fs_d_f12: mfc1 t3, $f12 mfc1 t0, $f13 b get_fs_d_doneget_fs_d_f14: mfc1 t3, $f14 mfc1 t0, $f15 b get_fs_d_doneget_fs_d_f16: mfc1 t3, $f16 mfc1 t0, $f17 b get_fs_d_doneget_fs_d_f18: mfc1 t3, $f18 mfc1 t0, $f19 b get_fs_d_doneget_fs_d_f20: mfc1 t3, $f20 mfc1 t0, $f21 b get_fs_d_doneget_fs_d_f22: mfc1 t3, $f22 mfc1 t0, $f23 b get_fs_d_doneget_fs_d_f24: mfc1 t3, $f24 mfc1 t0, $f25 b get_fs_d_doneget_fs_d_f26: mfc1 t3, $f26 mfc1 t0, $f27 b get_fs_d_doneget_fs_d_f28: mfc1 t3, $f28 mfc1 t0, $f29 b get_fs_d_doneget_fs_d_f30: mfc1 t3, $f30 mfc1 t0, $f31get_fs_d_done: srl t1, t0, 20 # get exponent and t1, t1, 0x7FF and t2, t0, 0xFFFFF # get fraction srl t0, t0, 31 # get sign bne t1, DEXP_INF, 1f # is it a signaling NAN? and v0, t2, DSIGNAL_NAN bne v0, zero, invalid_d1: j raEND(get_ft_fs_d)/*---------------------------------------------------------------------------- * get_cmp_s -- * * Read (single precision) the FS register (bits 15-11) and * the FT register (bits 20-16) and break up into fields. * This is an internal routine used by MachEmulateFP only. * * Results: * t0 contains the sign * t1 contains the (biased) exponent * t2 contains t⌨️ 快捷键说明
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