io870.h

一个桥接器87ch47仿真器的c的源程序

/* TC3 operation mode select */
#define	TC3M	0x01	/* TC3M=0: timer/event counter mode		*/
			/* TC3M=1: caputure				*/
/* TC3 source clock select */
#define	TC3CK	0x0c
#define	TC3CK00	0x00	/* TC3CK=00: internal clock fc/2^12 or fc/2^4	*/
#define	TC3CK01	0x04	/* TC3CK=01: internal clock fc/2^10 or fc/2^2	*/
#define	TC3CK10	0x08	/* TC3CK=10: internal clock fc/2^7		*/
#define	TC3CK11	0x0c	/* TC3CK=11: EXTERNal clock (TC3 pin input)	*/
/* TC3 start control */
#define	TC3S	0x10	/* TC3S=0: stop & clear				*/
			/* TC3S=1: start				*/
/* software capture control */
#define	SCAP3	0x40	/* SCAP3=0: -----				*/
			/* SCAP3=1: software capture			*/

/********************************************************
 *	TC5CR (timer/counter 4 control register)	*
 ********************************************************/
/* TC5 operating mode select */
#define	TC5M	0x03
#define	TC5M00	0x00	/* TC5M=00: timer/event counter mode		*/
#define	TC5M01	0x01	/* TC5M=01: reserved				*/
#define	TC5M10	0x02	/* TC5M=10: programmable divider output (PDO) mode   */
#define	TC5M11	0x03	/* TC5M=11: pulse width modulation (PWM) output mode */

/* TC5 source clock select */
#define	TC5CK	0x1c
#define	TC5CK000	0x00	/* reserved	*/
#define	TC5CK001	0x04	/* TC5CK=01: internal clock fc/2^7		*/
#define	TC5CK010	0x08	/* TC5CK=10: internal clock fc/2^5		*/
#define	TC5CK011	0x0c	/* TC5CK=10: internal clock fc/2^3		*/
#define	TC5CK100	0x10	/* TC5CK=00: internal clock fc/2^2		*/
#define	TC5CK101	0x14	/* TC5CK=01: internal clock fc/2^1		*/
#define	TC5CK110	0x08	/* TC5CK=10: internal clock fc			*/
#define	TC5CK111	0x1c	/* Treserved	*/

/* TC5 start control */
#define	TC5S	0x20	/* TC5S=0: stop & clear				*/
			/* TC5S=1: start				*/


/****************************************************************
 *	SIOCR1 (SIO control registers 1)		*
 ****************************************************************/
/* indicate transfer start/stop */
#define	SIOS		0x80	/* SIOS=0: stop			*/
				/* SIOS=1: start		*/
/* continue/about transfer */
#define	SIOINH		0x40	/* SIOINH=0: continue transfer	*/
				/* SIOINH=1: abort transfer
				   (automatically cleared after about)	*/
/* trancefer mode select */
#define	SIOM		0x38
#define	SIOM000		0x00	/* SIOM=000: 8-bit transmit mode	*/
#define	SIOM010		0x10	/* SIOM=010: 4-bit transmit mode	*/
#define	SIOM100		0x20	/* SIOM=100: 8-bit transmit/receive mode */
#define	SIOM101		0x28	/* SIOM=101: 8-bit receive mode		*/
#define	SIOM110		0x30	/* SIOM=110: 4-bit receive mode		*/
/* serial clock select */
#define	SCK		0x07
#define	SCK000		0x00	/* SCK=000: internal clock fc/2^13 or fs/2^5 */
#define	SCK001		0x01	/* SCK=001: internal clock fc/2^8	*/
#define	SCK010		0x02	/* SCK=010: internal clock fc/2^6	*/
#define	SCK011		0x03	/* SCK=011: internal clock fc/2^5	*/
#define	SCK111		0x07	/* SCK=111: EXTERNal clock		*/

/****************************************************************
 *	SIOCR2 (SIO control registers 2)		*
 ****************************************************************/
/* wait control */
#define	WAIT		0x18
#define	WAIT00		0x00	/* WAIT=00: Tf = TD	*/
#define	WAIT01		0x08	/* WAIT=01: Tf = 2TD	*/
#define	WAIT10		0x10	/* WAIT=10: Tf = 4TD	*/
#define	WAIT11		0x18	/* WAIT=11: Tf = 8TD	*/

/* number of transfer words */
#define	BUF		0x07
#define	BUF000		0x00	/* BUF=000 1 word transfer 0ff0h */
#define	BUF001		0x01	/* BUF=001 2 word transfer 0ff0-0ff1h*/
#define	BUF010		0x02	/* BUF=010 3 word transfer 0ff0-0ff2h*/
#define	BUF011		0x03	/* BUF=011 4 word transfer 0ff0-0ff3h*/
#define	BUF100		0x04	/* BUF=100 5 word transfer 0ff0-0ff4h*/
#define	BUF101		0x05	/* BUF=101 6 word transfer 0ff0-0ff5h*/
#define	BUF110		0x06	/* BUF=110 7 word transfer 0ff0-0ff6h*/
#define	BUF111		0x07	/* BUF=111 8 word transfer 0ff0-0ff7h*/

/****************************************************************
 *	SIOSR /  (SIO status registers)		*
 ****************************************************************/
/* serial transfer operating status monitor */
#define	SIOF		0x80	/* SIOF=0: transfer terminated */
				/* SIOF=1: transfer in process */

/* shift operating status monitor */
#define	SEF		0x40	/* SEF=0: shift operation terminated */
				/* SEF=1: shift operation in process */

/************************************************
 *	WDTCR1 (watchdog timer control)		*
 ************************************************/
/* watchdog timer control */
#define	WDTEN		0x80	/* WDTEN=0: disable		*/
				/* WDTEN=1: enable		*/
/* timming of detection */
#define	WDTT		0x06
#define	WDTT00		0x00	/* WDTT=00:2^25/fc or 2^17/fs	*/
#define	WDTT01		0x02	/* WDTT=01:2^23/fc or 2^15/fs	*/
#define	WDTT10		0x04	/* WDTT=10:2^21/fc or 2^13/fs	*/
#define	WDTT11		0x06	/* WDTT=11:2^19/fc or 2^11/fs	*/

/* watchdog timer output select */
#define	WDTOUT		0x01	/* WDTOUT=0: interrupt request	*/
				/* WDTOUT=1: reset output	*/

/************************************************
 *	WDTCR2 (watchdog timer control)		*
 ************************************************/
#define	WDTDI		0xb1	/* WDT Disable code		*/

#define	WDTCL		0x4e	/* WDT Clear code		*/


/*****************************************************
 *	TBTCR (time base timer control register)     *
 *****************************************************/
/*****************************
 * timing generator	     *
 *****************************/
/* selection of input clock to the 7th stage of the driver	*/
#define	DV7CK		0x10	/* DV7CK=0: fc/2^8	*/
				/* DV7CK=1; fs		*/

/*****************************
 * time base timer (TBT)     *
 *****************************/
/* time base timer enable/disable */
#define	TBTEN		0x08	/* TBTEN=0: disable 		*/
				/* TBTEN=1: enable		*/

/* time base timer interrupt frequency select */
#define	TBTCK		0x07
#define	TBTCK0		0x00	/* TBTCK=000: fc/2^23 or fs/2^15	*/
#define	TBTCK1		0x01	/* TBTCK=001: fc/2^21 or fs/2^13	*/
#define	TBTCK2		0x02	/* TBTCK=010: fc/2^16 or fs/2^8	*/
#define	TBTCK3		0x03	/* TBTCK=011: fc/2^14 or fs/2^6	*/
#define	TBTCK4		0x04	/* TBTCK=100: fc/2^13 or fs/2^5	*/
#define	TBTCK5		0x05	/* TBTCK=101: fc/2^12 or fs/2^4	*/
#define	TBTCK6		0x06	/* TBTCK=110: fc/2^11 or fs/2^3	*/
#define	TBTCK7		0x07	/* TBTCK=111: fc/2^9  or fs/2	*/

/*****************************
 * divider output (DVO)	     *
 *****************************/
/* driver output enable/disable */
#define	DVOEN		0x80	/* DVOEN=0: disable		*/
				/* DVOEN=1: enable		*/

/* driver output frequency selection */
#define	DVOCK		0x30
#define	DVOCK0		0x00	/* DVOCK=00: fc/2^13 or fs/2^5,	976Hz */
#define	DVOCK1		0x10	/* DVOCK=01: fc/2^12 or fs/2^4,	1953Hz*/
#define	DVOCK2		0x20	/* DVOCK=10: fc/2^11 or fs/2^3,	3906Hz*/
#define	DVOCK3		0x30	/* DVOCK=11: fc/2^10 or fs/2^2,	7812Hz*/


/**********************************************************
 *	EINTCR (EXTERNal interrupt control register)	  *
 **********************************************************/
/* noise reject time select */
#define	INT1NC		0x80	/* INT1NC=0: pulses of less than 63/fc[s] are
					     eliminated as noise	*/
				/* INT1NC=1: pulses of less than 15/fc[s] are
					     eliminated as noise	*/
/* P10/INT0 pin configration */
#define	INT0EN		0x40	/* INT0EN=0: P10 input/output port	*/
				/* INT0EN=1: INT0 pin (port P10 should be set to an input mode) */
/* INT4,3,2,1 edge select */
#define	INT4ES		0x10	/* 0: rising edge 	1: falling edge	*/
#define	INT3ES		0x08
#define	INT2ES		0x04
#define	INT1ES		0x02


/*****************************
 * stand-by control	     *
 *****************************/
/*****************************************************
 *	SYSCR1 (system control register 1)	     *
 *****************************************************/
/* STOP mode start */
#define	STOP		0x80	/* STOP=0: CPU core and peripherals remain achive		*/
				/* STOP=1: CPU core and peripherals are halted (start STOP mode)*/
/* release method for STOP mode	*/
#define	RELM		0x40	/* RELM=0: edge-sensitive release	*/
				/* RELM=1: level-sensitive release	*/
/* operating mode after STOP mode */
#define	RETM		0x20	/* RETM=0: return to NORMAL mode	*/
				/* RETM=1: return to SLOW mode		*/
/* port output control during STOP mode */
#define	OUTEN		0x10	/* OUTEN=0: high-impedance		*/
				/* OUTEN=1: remain unchanged		*/
/* warming-up time at releasing STOP mode */
#define	WUT		0x0c
#define	WUT00		0x00	/* WUT=00: 3*2^19/fc or 3*2^13/fs	*/
#define	WUT01		0x04	/* WUT=01:   2^19/fc or   2^13/fs	*/
#define	WUT10		0x08	/* WUT=10: reserved			*/
#define	WUT11		0x0c	/* WUT=11: reserved			*/

/*****************************************************
 *	SYSCR2 (system control register 2)	     *
 *****************************************************/
/* high-frequency oscillator control */
#define	XEN		0x80	/* XEN=0: turn off oscillation		*/
				/* XEN=1: turn on oscillation		*/
/* low-frequency oscillator control */
#define	XTEN		0x40	/* XTEN=0: turn off oscillation		*/
				/* XTEN=1: turn on oscillation		*/
/* main system clock select (write) /
   main system clock monitor (read)	*/
#define	SYSCK		0x20	/* SYSCK=0: high-frequency clock	*/
				/* SYSCK=1: low-frequency clock		*/
/* IDLE mode start */
#define	IDLE		0x10	/* IDLE=0: CPU and watchdog timer remain active	*/
				/* IDLE=1: CPU and watchdog timer are stopped
				   (start IDLE mode)			*/


/****************************************
 *	IL (interrupt latch)		*
 ****************************************/
#define	IL2		0x0004		/* interrupt latch Bit2		*/
#define	IL3		0x0008		/* interrupt latch Bit3		*/
#define	IL4		0x0010		/* interrupt latch Bit4		*/
#define	IL5		0x0020		/* interrupt latch Bit5		*/
#define	IL6		0x0040		/* interrupt latch Bit6		*/
#define	IL7		0x0080		/* interrupt latch Bit7		*/
#define	IL8		0x0100		/* interrupt latch Bit8		*/
#define	IL9		0x0200		/* interrupt latch Bit9		*/
#define	IL10		0x0400		/* interrupt latch Bit10	*/
#define	IL11		0x0800		/* interrupt latch Bit11	*/
#define	IL12		0x1000		/* interrupt latch Bit12	*/
#define	IL13		0x2000		/* interrupt latch Bit13	*/
#define	IL14		0x4000		/* interrupt latch Bit14	*/
#define	IL15		0x8000		/* interrupt latch Bit15	*/

/************************************************
 *      EIR (enable interrupt register)         *
 ************************************************/
#define	IMF		0x0001	/* interrupt master enable flag		  */
#define	EF4		0x0010	/* individual interrupt enable flag Bit4  */
#define	EF5		0x0020	/* individual interrupt enable flag Bit5  */
#define	EF6		0x0040	/* individual interrupt enable flag Bit6  */
#define	EF7		0x0080	/* individual interrupt enable flag Bit7  */
#define	EF8		0x0100	/* individual interrupt enable flag Bit8  */
#define	EF9		0x0200	/* individual interrupt enable flag Bit9  */
#define	EF10		0x0400	/* individual interrupt enable flag Bit10 */
#define	EF11		0x0800	/* individual interrupt enable flag Bit11 */
#define	EF12		0x1000	/* individual interrupt enable flag Bit12 */
#define	EF13		0x2000	/* individual interrupt enable flag Bit13 */
#define	EF14		0x4000	/* individual interrupt enable flag Bit14 */
#define	EF15		0x8000	/* individual interrupt enable flag Bit15 */


/*; ======================================================================
; [ Define MCU address ]
;  Modify the address to fit your program.
;======================================================================
StartAdr    equ    0xc000 ; Top address of start up routine
BaseSP      equ    0x023f ; Initial value of SP (highest stack address)
WDTCR1      equ    0x0034 ; Address of Watchdog Timer control register1
RAM_Top     equ    0x00c0 ; Start address of RAM (for RAM clear)
RAM_End     equ    0x023f ; End address of RAM (for RAM clear)
*/

/****************************************************************
 *	PSW/RBS (program status word/register bank selector)	*
 ****************************************************************/
#define	PSW_JF		0x80	/* JF */
#define	PSW_ZF		0x40	/* ZF */
#define	PSW_CF		0x20	/* CF */
#define	PSW_HF		0x10	/* HF */
#define	RBS3		0x08	/* RBS; bit3 */
#define	RBS2		0x04	/* RBS; bit2 */
#define	RBS1		0x02	/* RBS; bit1 */
#define	RBS0		0x01	/* RBS; bit0 */