boot.s

这是三星评估板ws310(CPU为S3c4510B)用的Bootloader.开发环境是SDT。

; 1.1.2.2
;**************************************************************
;*     File: boot.s                                           *
;*  Purpose: Application Startup Code                         *
;**************************************************************
;
; This code performs all the initialization required before
; branching to the main C application code.  It defines the
; ENTRY point, initializes the Stack Pointers for each mode,
; copies RO code and RW data from ROM to RAM and zero-initializes
; the ZI data areas used by the C code.
;
; This startup code is intended for use with hardware such as 
; the ARM PID board, where memory management maps an aliased 
; copy of the ROM at 0x04000000 to address zero on reset.
; Following reset, RAM is mapped into address zero, and the
; code then branches to execute from the real ROM.
	GET	mem.a
	GET	casia1.a
	INPORT  main_entry
 AREA    Boot, CODE, READONLY

; --- Define entry point
        ENTRY
Start_Boot
        EXPORT Start_Boot

; --- Continue execution from ROM rather than aliased copy at zero
;*********************************	
;mask all interrupt
;*********************************
	LDR 	R2,=0x14010380
	LDR	R3,=0x3ff302c
	STR	R2,[R3]
	LDR	R0,=0x400000
	ADR	R1,0
strcopy       
        ; r0 points to destination string
        ; r1 points to source string
        LDRB    r2, [r1],#1     ; load byte and update address
        STRB    r2, [r0],#1     ; store byte and update address;
        CMP     r2, #0x0  ; check for zero terminator
        BNE     strcopy ; keep going if not
	
	LDR 	R2,=0x10000380
	LDR	R3,=0x3ff302c
	STR	R2,[R3]
	

	LDR 	R2,=0x3fffff
	LDR	R3,=0x3ff4008
	STR	R2,[R3]

	

	LDR 	R2,=0xE7ffff90
	LDR	R3,=0x3ff0000
	STR	R2,[R3]


	LDR 	R2,=0x02000060
	LDR	R3,=0x3ff3014
	STR	R2,[R3]

	LDR 	R2,=0x14010380
	LDR	R3,=0x3ff302c
	STR	R2,[R3]

	LDR 	R2,=0xce338360
	LDR	R3,=0x3ff303c
	STR	R2,[R3]

;*******************************************************
;Disable all interrupt
;*******************************************************
	MRS	R0,CPSR
	BIC	R0,R0,#MODE_MASK
	ORR	R0,R0,#SUP_MODE
	ORR	R0,R0,#IBit
	ORR	R0,R0,#FBit 
	MSR	CPSR_cf,R0
	
;******************************************************
;Initialise system stack for different processor modes
;******************************************************
	MRS	r0, cpsr
	BIC	r0, r0, #LOCKOUT | MODE_MASK
	ORR	r2, r0, #USR_MODE	
	ORR	r1, r0, #LOCKOUT | FIQ_MODE

	MSR	cpsr_c, r1				;/* change to FIQ MODE */
	MSR	spsr_c, r2 				;/* set the SPSR under FIQ */
	LDR	sp, =FIQ_STACK				;/* set SP (R13) under FIQ */

	ORR	r1, r0, #LOCKOUT | IRQ_MODE
	MSR	cpsr_c, r1				;/* change to IRQ MODE */
	MSR	spsr_c, r2				;/* set the SPSR under IRQ */
	LDR	sp, =IRQ_STACK				;/* set SP (R13) under IRQ */

	ORR	r1, r0, #LOCKOUT | ABT_MODE
	MSR	cpsr_c, r1				;/* change to ABORT MODE */
	MSR	spsr_c, r2				;/* set the SPSR under ABORT */
	LDR	sp, =ABT_STACK				;/* set SP (R13) under ABORT */

	ORR	r1, r0, #LOCKOUT | UDF_MODE
	MSR	cpsr_c, r1				;/* change to Undefine MODE */
	MSR	spsr_c, r2				;/* set the SPSR under Undefine */
	LDR	sp, =UDF_STACK				;/* set SP (R13) under Undefine */

	ORR	r1, r0, #LOCKOUT | SUP_MODE
	MSR	cpsr_c, r1				;/* change to Superuser MODE */
	MSR	spsr_c, r2				;/* set the SPSR under super */ 
	LDR	sp, =SUP_STACK		

	MRS	r0, cpsr
	BIC	r0, r0, #LOCKOUT | MODE_MASK
	ORR	r1, r0, #USR_MODE	
	MSR	CPSR_cf,R0
	LDR	SP,=USR_STACK


;********************************************************
;Timer setting
;********************************************************
	LDR	R1,=0x3FF6000
	LDR	R0,=&01
	STR	R0,[R1]

	LDR	R1,=0x3FF6004
	LDR	R0,=&3FFFFFF
	STR	R0,[R1]

;********************************************************
;Mask off all IRQ sources
;********************************************************


	LDR	R1,=INTMOD
	LDR	R0,=&0
	STR	R0,[R1]
	BL	C_Entry

; If above subroutine ever returns, just sit in an endless loop
here    B       here

        END