ad_c.h

TIOMAP_L138的AD采样程序

#include<AD_H.h>

#define CHKBIT(dest,mask)     (dest & mask)
#define TGLBIT(dest,mask)     (dest ^= mask)
#define SETBIT(dest,mask)     (dest |= mask)
#define CLRBIT(dest,mask)     (dest &= ~mask)

//-----------------------------------------------------------------------------
// Global Variable Initializations
//-----------------------------------------------------------------------------
const uint32_t bitval_u32[32] =
{
   0x00000001, 0x00000002, 0x00000004, 0x00000008,
   0x00000010, 0x00000020, 0x00000040, 0x00000080,
   0x00000100, 0x00000200, 0x00000400, 0x00000800,
   0x00001000, 0x00002000, 0x00004000, 0x00008000,
   0x00010000, 0x00020000, 0x00040000, 0x00080000,
   0x00100000, 0x00200000, 0x00400000, 0x00800000,
   0x01000000, 0x02000000, 0x04000000, 0x08000000,
   0x10000000, 0x20000000, 0x40000000, 0x80000000
};

//-----------------------------------------------------------------------------
// Private Defines and Macros
//-----------------------------------------------------------------------------
#define GPIO_ODD_BANK_PIN_ADDER     (16)

void EVMOMAPL138_lpscTransition(psc_regs_t *psc, uint32_t in_domain, uint8_t in_module, uint8_t in_next_state)
{
   // spin until existing transitions are done.
   while (CHKBIT(psc->PTSTAT, in_domain)) {}

   // if we are already in the requested state...just return.
   if (CHKBIT(psc->MDSTAT[in_module], MASK_STATE) == in_next_state)
   {
      return;
   }

   // setup the transition...clear the bits before setting the next state.
   CLRBIT(psc->MDCTL[in_module], NEXT);
   SETBIT(psc->MDCTL[in_module], in_next_state);

   // kick off the transition.
   SETBIT(psc->PTCMD, in_domain);

   // spin until transition is done.
   while (CHKBIT(psc->PTSTAT, in_domain)) {}

   while (CHKBIT(psc->MDSTAT[in_module], MASK_STATE) != in_next_state) {}
}

void EVMOMAPL138_pinmuxConfig(uint32_t in_reg, uint32_t in_mask, uint32_t in_val)
{
   // unlock the system config registers.
   SYSCONFIG->KICKR[0] = KICK0R_UNLOCK;
   SYSCONFIG->KICKR[1] = KICK1R_UNLOCK;
   
   // make sure the pinmux register is cleared for the mask bits before
   // setting the value.
   CLRBIT(SYSCONFIG->PINMUX[in_reg], in_mask);
   SETBIT(SYSCONFIG->PINMUX[in_reg], in_val);
   
   // lock the system config registers.
   SYSCONFIG->KICKR[0] = KICK0R_LOCK;
   SYSCONFIG->KICKR[1] = KICK1R_LOCK;
}

static gpio_regs_t * getRegisterBankAndBit(uint32_t in_bank, uint8_t in_pin_num, uint32_t *reg_bit)
{
   gpio_regs_t *rtn;

   switch (in_bank)
   {
      case GPIO_BANK0:
         rtn = GPIO_BANK01;
         break;

      case GPIO_BANK1:
         rtn = GPIO_BANK01;
         in_pin_num += GPIO_ODD_BANK_PIN_ADDER;
         break;
      
      case GPIO_BANK2:
         rtn = GPIO_BANK23;
         break;
         
      case GPIO_BANK3:
         rtn = GPIO_BANK23;
         in_pin_num += GPIO_ODD_BANK_PIN_ADDER;
         break;
      
      case GPIO_BANK4:
         rtn = GPIO_BANK45;
         break;
         
      case GPIO_BANK5:
         rtn = GPIO_BANK45;
         in_pin_num += GPIO_ODD_BANK_PIN_ADDER;
         break;
      
      case GPIO_BANK6:
         rtn = GPIO_BANK67;
         break;
         
      case GPIO_BANK7:
         rtn = GPIO_BANK67;
         in_pin_num += GPIO_ODD_BANK_PIN_ADDER;
         break;

      case GPIO_BANK8:
         rtn = GPIO_BANK8_;
         break;
   }
   
   *reg_bit = bitval_u32[in_pin_num];

   return (rtn);
}


uint32_t GPIO_setDir(uint32_t in_bank, uint8_t in_pin_num, uint8_t in_dir)
{
   uint32_t rtn = ERR_INVALID_PARAMETER;

   if ((in_bank < MAX_GPIO_BANK_NUM) && (in_pin_num < MAX_GPIO_PIN_NUM))
   {
      gpio_regs_t *gpio_bank;
      uint32_t gpio_bit;

      // get the register bank and bitmask for the input bank and pin.
      gpio_bank = getRegisterBankAndBit(in_bank, in_pin_num, &gpio_bit);

      if (GPIO_OUTPUT == in_dir)
      {
         // clear the bit to config pin for output.
         CLRBIT(gpio_bank->DIR, gpio_bit);
      }
      else
      {
         // set the bit to config pin for input.
         SETBIT(gpio_bank->DIR, gpio_bit);
      }
      
      rtn = ERR_NO_ERROR;
   }
   
   return (rtn);
}


//-----------------------------------------------------------------------------
// \brief   halts execution for "in_delay" number of microseconds.
//
// \param   uint32_t in_delay - the number of us to delay.
//
// \return  none.
//-----------------------------------------------------------------------------
void USTIMER_delay(uint32_t in_delay)
{
   // stop the timer, clear int stat, and clear timer value.
   CLRBIT(TMR1->TGCR, TIM34RS);
   TMR1->TCR = 0x00000000;
   SETBIT(TMR1->INTCTLSTAT, PRDINTSTAT34);
   TMR1->TIM34 = 0x00000000;

   // setup compare time.
   // NOTE: not checking for possible rollover here...do not pass in a
   // value > 0x7FFFFFFF....would result in a much shorter delay than expected.
   TMR1->PRD34 = TICKS_PER_US * in_delay;
   
   // start timer1 - 3:4 to run once up to the period.
   SETBIT(TMR1->TCR, ENAMODE34_ONETIME);
   SETBIT(TMR1->TGCR, TIM34RS);
   
   // wait for the signal that we have hit our period.
   while (!CHKBIT(TMR1->INTCTLSTAT, PRDINTSTAT34))
   {
      asm("nop");
   }
//   uint32_t i;
//   for (i = 0; i < in_delay * 1; i++) {}
}