ad_h.h

TIOMAP_L138的AD采样程序

#define PINMUX_EMIFA_NOR_VAL_0      (0x11000000)
#define PINMUX_EMIFA_NOR_REG_1      (6)
#define PINMUX_EMIFA_NOR_MASK_1     (0x0F00000F)
#define PINMUX_EMIFA_NOR_VAL_1      (0x01000001)
#define PINMUX_EMIFA_NOR_REG_2      (7)
#define PINMUX_EMIFA_NOR_MASK_2     (0x0FFF000F)
#define PINMUX_EMIFA_NOR_VAL_2      (0x01110001)
#define PINMUX_EMIFA_NOR_REG_3      (8)
#define PINMUX_EMIFA_NOR_MASK_3     (0xFFFFFFFF)
#define PINMUX_EMIFA_NOR_VAL_3      (0x11111111)
#define PINMUX_EMIFA_NOR_REG_4      (9)
#define PINMUX_EMIFA_NOR_MASK_4     (0xFFFFFFFF)
#define PINMUX_EMIFA_NOR_VAL_4      (0x11111111)
#define PINMUX_EMIFA_NOR_REG_5      (10)
#define PINMUX_EMIFA_NOR_MASK_5     (0xFFFFFFFF)
#define PINMUX_EMIFA_NOR_VAL_5      (0x11111111)
#define PINMUX_EMIFA_NOR_REG_6      (11)
#define PINMUX_EMIFA_NOR_MASK_6     (0xFFFFFFFF)
#define PINMUX_EMIFA_NOR_VAL_6      (0x11111111)
#define PINMUX_EMIFA_NOR_REG_7      (12)
#define PINMUX_EMIFA_NOR_MASK_7     (0xFFFFFFFF)
#define PINMUX_EMIFA_NOR_VAL_7      (0x11111111)

struct EDMA3CC_PaRAM
{
   volatile uint32_t OPT;
   volatile uint16_t *SRC;
   volatile uint32_t A_B_CNT;
   volatile uint16_t *DST;
   volatile uint32_t SRC_DST_BIDX;
   volatile uint32_t LINK_BCNTRLD;
   volatile uint32_t SRC_DST_CIDX;
   volatile uint32_t CCNT;
};

#define EDMA3_GPIO2			(struct EDMA3CC_PaRAM *)ioremap(GPIO2_PARAM_BASE,sizeof(struct EDMA3CC_PaRAM))
#define EDMA3CC_PaRAM127	(struct EDMA3CC_PaRAM *)ioremap(PaRAM127_PARAM_BASE,sizeof(struct EDMA3CC_PaRAM))
#define EDMA3_0_ESR		*(uint32_t *)ioremap(0x01C01010,sizeof(uint32_t))
#define EDMA3_0_EECR	*(uint32_t *)ioremap(0x01C01028,sizeof(uint32_t))
#define EDMA3_0_EESR	*(uint32_t *)ioremap(0x01C01030,sizeof(uint32_t))
#define EDMA3_0_IECR	*(uint32_t *)ioremap(0x01C01058,sizeof(uint32_t))
#define EDMA3_0_IESR	*(uint32_t *)ioremap(0x01C01060,sizeof(uint32_t))
#define EDMA3_0_IPR		*(uint32_t *)ioremap(0x01C01068,sizeof(uint32_t))
#define EDMA3_0_ICR		*(uint32_t *)ioremap(0x01C01070,sizeof(uint32_t))
#define EDMA3_0_EMCR	*(uint32_t *)ioremap(0x01C00308,sizeof(uint32_t)) 
#define EDMA3_0_SECR	*(uint32_t *)ioremap(0x01C01040,sizeof(uint32_t))
#define EDMA3_0_ECR		*(uint32_t *)ioremap(0x01C01008,sizeof(uint32_t))

#define AD_DATA		(volatile uint16_t *)ioremap(0x64000020,sizeof(uint16_t))
#define AD_RESET	(*(uint16_t *)ioremap(0x64000030,sizeof(uint32_t))) = 1;
#define AD_RELEASE	(*(uint16_t *)ioremap(0x64000030,sizeof(uint32_t))) = 0;
#define LED			*(uint16_t *)ioremap(0x64000040,sizeof(uint16_t))
#define AD_LENGTH	410 

//-----------------------------------------------------------------------------
// Register Structure & Defines
//-----------------------------------------------------------------------------
typedef struct
{
  volatile uint32_t REVID;          // 0x0000
  volatile uint32_t RSVD0[5];       // 0x0004
  volatile uint32_t INTEVAL;        // 0x0018
  volatile uint32_t RSVD1[9];       // 0x001C
  volatile uint32_t MERRPR0;        // 0x0040
  volatile uint32_t RSVD2[3];       // 0x0044
  volatile uint32_t MERRCR0;        // 0x0050
  volatile uint32_t RSVD3[3];       // 0x0054
  volatile uint32_t PERRPR;         // 0x0060
  volatile uint32_t RSVD4;          // 0x0064
  volatile uint32_t PERRCR;         // 0x0068
  volatile uint32_t RSVD5[45];      // 0x006C
  volatile uint32_t PTCMD;          // 0x0120
  volatile uint32_t RSVD6;          // 0x0124
  volatile uint32_t PTSTAT;         // 0x0128
  volatile uint32_t RSVD7[53];      // 0x012C
  volatile uint32_t PDSTAT0;        // 0x0200
  volatile uint32_t PDSTAT1;        // 0x0204
  volatile uint32_t RSVD8[62];      // 0x0208
  volatile uint32_t PDCTL0;         // 0x0300
  volatile uint32_t PDCTL1;         // 0x0304
  volatile uint32_t RSVD9[62];      // 0x0308
  volatile uint32_t PDCFG0;         // 0x0400
  volatile uint32_t PDCFG1;         // 0x0404
  volatile uint32_t RSVD10[254];    // 0x0408
  volatile uint32_t MDSTAT[32];     // 0x0800
  volatile uint32_t RSVD11[96];     // 0x0880
  volatile uint32_t MDCTL[32];      // 0x0A00
} psc_regs_t;

#define PSC0_REG_BASE         (0x01C10000)

// psc0 lpsc defines.
#define LPSC_EMIFA         (3)

// domain defines.
#define DOMAIN0         (0x00000001)

// psc module status register defines.
#define MASK_STATE               (0x0000003F)

// psc module control register defines.
#define NEXT                     (0x00000007)   // bits 0-2.

// psc module next states.
#define PSC_ENABLE               (0x00000003)

// define the power and sleep config modules.
#define PSC0            ((psc_regs_t *)ioremap(PSC0_REG_BASE,sizeof(psc_regs_t)))

typedef struct
{
   volatile uint32_t REVID;            // 0x0000
   volatile uint32_t RSVD0;            // 0x0004
   volatile uint32_t DIEIDR[4];        // 0x0008
   volatile uint32_t RSVD1[2];         // 0x0018
   volatile uint32_t BOOTCFG;          // 0x0020
   volatile uint32_t RSVD2[5];         // 0x0024
   volatile uint32_t KICKR[2];         // 0x0038
   volatile uint32_t HOST0CFG;         // 0x0040
   volatile uint32_t HOST1CFG;         // 0x0044
   volatile uint32_t RSVD3[38];        // 0x0048
   volatile uint32_t IRAWSTAT;         // 0x00E0
   volatile uint32_t IENSTAT;          // 0x00E4
   volatile uint32_t IENSET;           // 0x00E8
   volatile uint32_t IENCLR;           // 0x00EC
   volatile uint32_t EOI;              // 0x00F0
   volatile uint32_t FLTADDRR;         // 0x00F4
   volatile uint32_t FLTSTAT;          // 0x00F8
   volatile uint32_t RSVD4[5];         // 0x00FC
   volatile uint32_t MSTPRI[3];        // 0x0110
   volatile uint32_t RSVD5;            // 0x011C
   volatile uint32_t PINMUX[20];       // 0x0120
   volatile uint32_t SUSPSRC;          // 0x0170
   volatile uint32_t CHIPSIG;          // 0x0174
   volatile uint32_t CHIPSIG_CLR;      // 0x0178
   volatile uint32_t CFGCHIP[5];       // 0x017C
} sysconfig_regs_t;

// system config registers
//-----------------------------------------------------------------------------
#define SYSCONFIG_REG_BASE    (0x01C14000)

// define the one and only system config module.
#define SYSCONFIG          ((sysconfig_regs_t *)ioremap(SYSCONFIG_REG_BASE,sizeof(sysconfig_regs_t)))

// unlock/lock kick registers defines.
#define KICK0R_UNLOCK      (0x83E70B13)
#define KICK1R_UNLOCK      (0x95A4F1E0)
#define KICK0R_LOCK        (0x00000000)
#define KICK1R_LOCK        (0x00000000)

// Register Structure & Defines
//-----------------------------------------------------------------------------
typedef struct
{
   volatile uint32_t REVID;               // 0x0000
   volatile uint32_t AWCC;                // 0x0004
   volatile uint32_t SDCR;                // 0x0008
   volatile uint32_t SDRCR;               // 0x000C
   volatile uint32_t CE2CFG;              // 0x0010
   volatile uint32_t CE3CFG;              // 0x0014
   volatile uint32_t CE4CFG;              // 0x0018
   volatile uint32_t CE5CFG;              // 0x001C
   volatile uint32_t SDTIMR;              // 0x0020
   volatile uint32_t RSVD0[6];            // 0x0024
   volatile uint32_t SDSRETR;             // 0x003C
   volatile uint32_t INTRAW;              // 0x0040
   volatile uint32_t INTMASK;             // 0x0044
   volatile uint32_t INTMASKSET;          // 0x0048
   volatile uint32_t INTMASKCLR;          // 0x004C
   volatile uint32_t RSVD1[4];            // 0x0050
   volatile uint32_t NANDFCR;             // 0x0060
   volatile uint32_t NANDFSR;             // 0x0064
   volatile uint32_t PMCR;                // 0x0068
   volatile uint32_t NANDF1ECC;           // 0x0070
   volatile uint32_t NANDF2ECC;           // 0x0074
   volatile uint32_t NANDF3ECC;           // 0x0078
   volatile uint32_t NANDF4ECC;           // 0x007C
   volatile uint32_t RSVD2[15];           // 0x0080
   volatile uint32_t NAND4BITECCLOAD;     // 0x00BC
   volatile uint32_t NAND4BITECC1;        // 0x00C0
   volatile uint32_t NAND4BITECC2;        // 0x00C4
   volatile uint32_t NAND4BITECC3;        // 0x00C8
   volatile uint32_t NAND4BITECC4;        // 0x00CC
   volatile uint32_t NANDERRADDR1;        // 0x00D0
   volatile uint32_t NANDERRADDR2;        // 0x00D4
   volatile uint32_t NANDERRVAL1;         // 0x00D8
   volatile uint32_t NANDERRVAL2;         // 0x00DC
} emifa_regs_t;

// EMIFA registers
//-----------------------------------------------------------------------------
#define EMIFA_REG_BASE        (0x68000000)

#define EMIFA        ((emifa_regs_t *)ioremap(EMIFA_REG_BASE,sizeof(emifa_regs_t)))

// Return Error Defines
//-----------------------------------------------------------------------------
#define ERR_NO_ERROR             (0)
#define ERR_INVALID_PARAMETER    (4)

//-------------------------------------------------------------------------------
//public Function  Prototypes
//---------------------------------------------------------------------------------
void TEST_ad(void);
void AD_init();
void DMAconfig();
void EVMOMAPL138_lpscTransition(psc_regs_t *psc, uint32_t in_domain, uint8_t in_module, uint8_t in_next_state); 
void EVMOMAPL138_pinmuxConfig(uint32_t in_reg, uint32_t in_mask, uint32_t in_val);
static gpio_regs_t * getRegisterBankAndBit(uint32_t in_bank, uint8_t in_pin_num, uint32_t *reg_bit);
uint32_t GPIO_setDir(uint32_t in_bank, uint8_t in_pin_num, uint8_t in_dir);
void USTIMER_delay(uint32_t in_delay);