ad_h.h

TIOMAP_L138的AD采样程序

//----------------------------------------------------------------------------
// \file    types.h
// \brief   .
//
//----------------------------------------------------------------------------
#include<linux/init.h>
#include<linux/module.h>
#include<linux/kernel.h>
#include<linux/delay.h>
#include<linux/proc_fs.h>
#include<hardware.h>
#include<linux/cdev.h>
#include<linux/mm.h>
#include<linux/sched.h>
#include<linux/types.h>
#include<linux/fs.h>
#include<linux/errno.h>
#include<asm/io.h>
#include<asm/system.h>
#include<asm/uaccess.h>


#ifndef TYPES_H
#define TYPES_H

//----------------------------------------------------------------------------
// datatypes
//----------------------------------------------------------------------------
typedef unsigned char   uint8_t;
typedef unsigned short  uint16_t;
typedef unsigned int    uint32_t;
typedef unsigned long   ulong_t;
typedef signed char     int8_t;
typedef signed short    int16_t;
typedef signed int      int32_t;
typedef signed long     long_t;

typedef enum 
{
	false = 0,
	true = 1
}bool_e; 


//-----------------------------------------------------------------------------
// Register Structure & Defines
//-----------------------------------------------------------------------------
typedef struct
{
    volatile uint32_t REV;             // 0x0000
    volatile uint32_t EMUMGT;          // 0x0004
    volatile uint32_t GPINT_GPEN;      // 0x0008
    volatile uint32_t GPDATA_GPDIR;    // 0x000C
    volatile uint32_t TIM12;           // 0x0010
    volatile uint32_t TIM34;           // 0x0014
    volatile uint32_t PRD12;           // 0x0018
    volatile uint32_t PRD34;           // 0x001C
    volatile uint32_t TCR;             // 0x0020
    volatile uint32_t TGCR;            // 0x0024
    volatile uint32_t WDTCR;           // 0x0028
    volatile uint32_t RSVD0[2];        // 0x002C
    volatile uint32_t REL12;           // 0x0034
    volatile uint32_t REL34;           // 0x0038
    volatile uint32_t CAP12;           // 0x003C
    volatile uint32_t CAP34;           // 0x0040
    volatile uint32_t INTCTLSTAT;      // 0x0044
    volatile uint32_t RSVD1[6];        // 0x0048
    volatile uint32_t CMP0;            // 0x0060
    volatile uint32_t CMP1;            // 0x0064
    volatile uint32_t CMP2;            // 0x0068
    volatile uint32_t CMP3;            // 0x006C
    volatile uint32_t CMP4;            // 0x0070
    volatile uint32_t CMP5;            // 0x0074
    volatile uint32_t CMP6;            // 0x0078
    volatile uint32_t CMP7;            // 0x007C
} timer_regs_t;

//-----------------------------------------------------------------------------
// Timer registers
//-----------------------------------------------------------------------------
#define TIMER0_REG_BASE       (0x01C20000)
#define TIMER1_REG_BASE       (0x01C21000)


// define all the available timer peripherals for the processor.
#define TMR0            ((timer_regs_t *)ioremap(TIMER0_REG_BASE,sizeof(timer_regs_t)))
#define TMR1            ((timer_regs_t *)ioremap(TIMER1_REG_BASE,sizeof(timer_regs_t)))


// bitmask defines for INTCTLSTAT.
#define PRDINTSTAT34             (0x00020000)   // bit 17

#define DELAY_HALF_SEC     (500000)    // in us
#define DELAY_10TH_SEC     (100000)    //in us

// bitmask defines for TGCR.
#define TIM34RS                  (0x00000002)   // bit 1

//-----------------------------------------------------------------------------
// Private Defines and Macros
//-----------------------------------------------------------------------------
#define TICKS_PER_US    (2)

// bitmask defines for TCR.
#define ENAMODE34_ONETIME        (0x00400000)   // bit 22

// bitmask defines for TGCR.
#define TIM34RS                  (0x00000002)   // bit 1


//-----------------------------------------------------------------------------
// Register Structure & Defines
//-----------------------------------------------------------------------------
typedef struct
{
   volatile uint32_t DIR;
   volatile uint32_t OUT_DATA;
   volatile uint32_t SET_DATA;
   volatile uint32_t CLR_DATA;
   volatile uint32_t IN_DATA;
   volatile uint32_t SET_RIS_TRIG;
   volatile uint32_t CLR_RIS_TRIG;
   volatile uint32_t SET_FAL_TRIG;
   volatile uint32_t CLR_FAL_TRIG;
   volatile uint32_t IRQ_STAT;
} gpio_regs_t;

//-----------------------------------------------------------------------------
// GPIO registers
//-----------------------------------------------------------------------------
#define GPIO_REG_BASE         (0x01E26000)
#define GPIO_BANK_OFFSET      (0x28)

#define GPIO_REV              (GPIO_REG_BASE)
#define GPIO_BINTEN           (GPIO_REG_BASE + 0x08)

#define GPIO_BANK01_BASE      (GPIO_REG_BASE + 0x10)
#define GPIO_BANK23_BASE      (GPIO_BANK01_BASE + GPIO_BANK_OFFSET)
#define GPIO_BANK45_BASE      (GPIO_BANK23_BASE + GPIO_BANK_OFFSET)
#define GPIO_BANK67_BASE      (GPIO_BANK45_BASE + GPIO_BANK_OFFSET)
#define GPIO_BANK8_BASE       (GPIO_BANK67_BASE + GPIO_BANK_OFFSET)

#define GPIO_BUFF_OE_BANK        (2)
#define GPIO_BUFF_OE_PIN         (6)
#define PINMUX_GPIO_BUFF_OE_REG  (6)
#define PINMUX_GPIO_BUFF_OE_MASK (0x000000F0)
#define PINMUX_GPIO_BUFF_OE_VAL  (0x00000080)


// define all the available gpio peripherals for the processor.
#define GPIO_BANK01              ((gpio_regs_t *)ioremap(GPIO_BANK01_BASE,sizeof(gpio_regs_t)))
#define GPIO_BANK23              ((gpio_regs_t *)ioremap(GPIO_BANK23_BASE,sizeof(gpio_regs_t)))
#define GPIO_BANK45              ((gpio_regs_t *)ioremap(GPIO_BANK45_BASE,sizeof(gpio_regs_t)))
#define GPIO_BANK67              ((gpio_regs_t *)ioremap(GPIO_BANK67_BASE,sizeof(gpio_regs_t)))
#define GPIO_BANK8_              ((gpio_regs_t *)ioremap(GPIO_BANK8_BASE,sizeof(gpio_regs_t)))

//-----------------------------------------------------------------------------
// Public Defines and Macros
//-----------------------------------------------------------------------------
#define GPIO_BANK0            (0)
#define GPIO_BANK1            (1)
#define GPIO_BANK2            (2)
#define GPIO_BANK3            (3)
#define GPIO_BANK4            (4)
#define GPIO_BANK5            (5)
#define GPIO_BANK6            (6)
#define GPIO_BANK7            (7)
#define GPIO_BANK8            (8)
#define MAX_GPIO_BANK_NUM     (9)

#define GPIO_PIN0             (0)
#define GPIO_PIN1             (1)
#define GPIO_PIN2             (2)
#define GPIO_PIN3             (3)
#define GPIO_PIN4             (4)
#define GPIO_PIN5             (5)
#define GPIO_PIN6             (6)
#define GPIO_PIN7             (7)
#define GPIO_PIN8             (8)
#define GPIO_PIN9             (9)
#define GPIO_PIN10            (10)
#define GPIO_PIN11            (11)
#define GPIO_PIN12            (12)
#define GPIO_PIN13            (13)
#define GPIO_PIN14            (14)
#define GPIO_PIN15            (15)
#define MAX_GPIO_PIN_NUM      (16)

#define GPIO_OUTPUT           (0)
#define GPIO_INPUT            (1)

#define OUTPUT_LOW            (0)
#define OUTPUT_HIGH           (1)

//GPIO pinmux
#define PINMUX_AD_INT_EN_REG	 (6)
#define PINMUX_AD_INT_EN_MASK	 (0xF0000000)
#define PINMUX_AD_INT_EN_VAL	 (0x80000000)

#define CLR_RIS_TRIG23	*(uint32_t *)ioremap(0x01E26050,sizeof(uint32_t))
#define SET_FAL_TRIG23	*(uint32_t *)ioremap(0x01E26054,sizeof(uint32_t))
#define BINTEN			*(uint32_t *)ioremap(0x01E26008,sizeof(uint32_t))
#define INTSTAT23		*(uint32_t *)ioremap(0x01E2605C,sizeof(uint32_t))
#define GPIO2_PARAM_BASE             0x01C042C0
#define PaRAM127_PARAM_BASE          0x01C04FE0

#define AD_EDMA_START	BINTEN |= (1 << GPIO_BANK2);	//Enable GP2 Bank Interrupt



#endif
/*	CPU registers					*/
extern cregister volatile unsigned int CSR;  /* Control Status Register  */
extern cregister volatile unsigned int IER;    
extern cregister volatile unsigned int ISTP; 


// emifa nor pinmux defines.
#define PINMUX_EMIFA_NOR_REG_0      (5)
#define PINMUX_EMIFA_NOR_MASK_0     (0xFF000000)