📄 fet410_fll02.s43
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#include "msp430x41x.h"; MSP430x41x Standard Definitions
;*******************************************************************************
; MSP-FET430P410 Demo - FLL+ clock, runs internal DCO at 8Mhz
;
; Description: This program demostrates setting the internalDCO to run at 8Mhz
; with auto-calibration by the FLL+.
; ACLK = LFXT1 = 32768, MCLK = SMCLK = DCOCLK = (n+1) x 2 x ACLK
; //*An external watch crystal is required on XIN/XOUT for ACLK*//
;
; MSP430F413
; -----------------
; /|\| XIN|-
; | | | 32kHz
; --|RST XOUT|-
; | |
; | P1.1|--> MCLK = 8Mhz
; | |
; | P1.5|--> ACLK = 32khz
; | |
;
; B. Merritt - meb
; Texas Instruments Inc.
; February 2002
;-----------------------------------------------------------------------------
ORG 0E000h ;program Start
;-----------------------------------------------------------------------------
RESET mov.w #300h,SP ;initialize stackpointer
SetupWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ;stop WDT
SetupFLL2 bis.b #FN_4,&SCFI0 ; x2 DCO, 8MHz nominal DCO
bis.b #DCOPLUS+XCAP14PF,&FLL_CTL0 ; DCO+, configure load caps
mov.b #121,&SCFQCTL ;(121+1) x 2 x 32768 = 7.99 Mhz
SetupPorts bis.b #022h,&P1DIR ;P1.1 & P1.5 to output direction
bis.b #022h,&P1SEL ;P1.1 & P1.5 to output MCLK & ACLK
;
Mainloop jmp Mainloop ;loop with CPU running
;
;-----------------------------------------------------------------------------
; MSP430F41x interrupt vectors used
;-----------------------------------------------------------------------------
ORG 0FFFEh ; MSP430 RESET Vector
DW RESET ;
END
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