📄 fet410_clks.s43
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#include "msp430x41x.h"
;******************************************************************************
; MSP-FET430P410 Demo - FLL+ Output MCLK, ACLK Using 32k XTAL and DCO
;
; Description; This program will output the system MCLK and ACLK.
; ACLK = LFXT1 = 32768, MCLK = DCO = 32xACLK 1.048576MHz
; //*An external watch crystal is required on XIN/XOUT for ACLK*//
;
; MSP430F413
; -----------------
; /|\| XIN|-
; | | | 32kHz
; --|RST XOUT|-
; | |
; | P1.1|-->MCLK 1048576
; | P1.5|-->ACLK 32kHz
;
; M.Buccini
; Texas Instruments, Inc
; January 2002
;******************************************************************************
;------------------------------------------------------------------------------
ORG 0E000h ; Program Start
;------------------------------------------------------------------------------
RESET mov.w #300h,SP ; Initialize stackpointer
StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
SetupFLL bis.b #XCAP14PF,&FLL_CTL0 ; Configure load caps
SetupP1 bis.b #022h,&P1DIR ; P1.1 and P1.5 output direction
bis.b #022h,&P1SEL ; P1.1 and P1.5 option select
;
Mainloop jmp Mainloop ;
;
;-----------------------------------------------------------------------------
; Interrupt Vectors Used MSP430F41x
;-----------------------------------------------------------------------------
ORG 0FFFEh ; MSP430 RESET Vector
DW RESET ;
END
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