main.asm

基于TMS320LF240采用 pwm方式控制直流电机调速

;***********************************************************************
; File Name: TMS320x240 Example Code
; Originator:jzming
; Tianhuang technology dsp development group.
; Description:This Program is to control a dc motor with variable speed. 
; 
;***********************************************************************
	.include	"x24x.h"
;=======================================================================
_stop		.usect	".blk0",1
ad_res_0	.usect	".blk0",1
ad_res_1	.usect	".blk0",1 
;=======================================================================
			.bss GPR0,1 ;General purpose register.
;=======================================================================
	.global	_c_int0,
	.ref	sys_int
	.def	adc_int,pdpint	
;=======================================================================
; C O D E  - starts here
;=======================================================================
		.text
_c_int0:
;
	LDP		#00E0h
	SPLK	#006Fh, WDCR	;disable watchdog w/max. overflow 
	KICK_DOG				;Reset watchdog counter
;
	CALL	sys_int			;
;
	LDP		#_stop
	SPLK	#0H,_stop		;
;
	CALL	init_pwm
;
	CALL	init_adc
;
	CALL	start_pwm
;   
	CLRC	INTM
loop:	
;
	LDP		#_stop
	BIT		_stop,15
	BCND	loop,NTC
;=================================================================================						;beginning and continue.
dead_loop:
	B	dead_loop		;dead loop 	
;---------------------------------------------------------------------------------
init_pwm:
;
	CLRC    SXM
	LDP     #0e8h
	LACC    GPTCON				; General-purpose timer control register
	OR      #0180H              ; mask for enabling ADC start on GPT1
	AND     #0FF7FH             ; mask for enabling ADC start on GPT1 Period Event
	SACL    GPTCON              ;seting T1 period interrupt flag, set T1 period interrup flag
								; to start A/D conversion
; 
	SPLK	#03FFH,T1PR        ;T1PER =03FFH pwm period
;
	LDP     #0E8H
	LACC    #0h,0
	SACL    T1CNT				;T1CNT=0
;
	SACL    DBTCON              ;DBTCON_value=0
	LACC    #0380H,0
	SACL    ACTR				; Active high/low states of PWM outputs in
								; upper/lower legs (0x0f38h)
	LACC    #0h,0           		; 
	SACL    CMPR1               ; Compare Channel 2 Threshold =0
	SACL    CMPR2               ; Compare Channel 2 Threshold =0
	SACL    CMPR3               ; Compare Channel 3 Threshold =0
	LACC    #2800H,0            ; 
	SACL    T1CON               ;timer in continuous up-down mode for symmetric PWM TIM_CONT_UP_DN=2800h
	LACC    #07H             	;
	SACL    COMCON				;full compare unit works in sym/asym PWM mode
	SETC    SXM                 ;SXM=1
;
	LDP     #0h
	LACL    IMR
	OR      #02h,0
	SACL    IMR 				;set IMR bit1
;
	LDP		#0E8H
	LACL	EVIMRA
	OR		#0001H
	SACL	EVIMRA		; enable PDPINT (activate PDPINT interrupt generation)
	RET
;====================================================================================
init_adc:						;
;
	CLRC    SXM					;
	LDP     #0E0h				;7000h
	LACC    #0400H,0	       	; 400h==ACC
	SACL    ADCTRL2				; enable conversion start by ev         
							; ADCTRL2 can set the ADC conversion to synchronize	 
							; with an event manager signal or with an external signal. 
							; It also provides status for data registers FIFO1 and 2.
							; EVENT manager SOC mask bit. enable conversion start by ev 
	LACC    #0DA3EH,0			;
	SACL    ADCTRL1         ; ADC1 and ADC2 enable. initialize channel 11 and channel 4
							;adcimstart=0,no action.
							;ADCIN7 - reads inverter REF
							;ADCIN11 - reads inverter V low-leg current
;
	LDP     #0h
	LACL    IMR
	OR      #20h,0
	SACL    IMR 			;set IMR bit5
;	
	SETC    SXM
	RET
;====================================================================================
start_pwm:
; enable compare opration
	LDP     #0e8h			; 
	LACL    COMCON
	OR      #8000h,0
	SACL    COMCON
; full compare output pin are not in the high-impedance
; they are enable
	LACL    COMCON
	OR      #200h,0
	SACL    COMCON
; enable T1 timer operations
	LACL    T1CON
	OR      #40h,0
	SACL    T1CON
;
	RET
;====================================================================================
adc_int:
;
	LDP     #0e0h           ;	 
	LACC    SYSIVR			;Load peripheral INT vector address
;   
	CLRC	SXM
	LDP     #0E0h
	LACC    ADCFIFO1,10		;
	LDP     #ad_res_0		;
	SACH    ad_res_0		;
	LACL	ad_res_0
	LDP		#0E8H
	SACL	CMPR2
	LDP     #0E0h			;
	LACC    ADCFIFO2,10		;
	LDP     #ad_res_1       ;
	SACH    ad_res_1		;
	LACL	ad_res_1
	LDP		#0E8H
	SACL	CMPR1	
;
	CLRC    INTM
	RET
;==================================================================================
pdpint:
	LDP     #0e8h           ;	
	LACC    EVIVRA			;Load peripheral pdp vector address
;
	LDP		#0E1H
	LACL	OCRA
	AND		#0EFFFH
	SACL	OCRA
;	
	LDP		#0E1H
	LACL	PBDATDIR
	OR		#1000H
	AND		#0FFEFH
	SACL	PBDATDIR
;
	B		dead_loop