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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"><html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1"><title>Procyon ARMlib-LPC2100: lpcUART.h Source File</title><link href="dox.css" rel="stylesheet" type="text/css"></head><body><!-- Generated by Doxygen 1.3.6 --><div class="qindex"><a class="qindex" href="main.html">Main Page</a> | <a class="qindex" href="files.html">File List</a> | <a class="qindex" href="globals.html">Globals</a></div><h1>lpcUART.h</h1><div class="fragment"><pre>00001 <span class="comment">/******************************************************************************</span>00002 <span class="comment"> *</span>00003 <span class="comment"> * $RCSfile: $</span>00004 <span class="comment"> * $Revision: $</span>00005 <span class="comment"> *</span>00006 <span class="comment"> * Header file for Philips LPC ARM Processors.</span>00007 <span class="comment"> * Copyright 2004 R O SoftWare</span>00008 <span class="comment"> *</span>00009 <span class="comment"> * No guarantees, warrantees, or promises, implied or otherwise.</span>00010 <span class="comment"> * May be used for hobby or commercial purposes provided copyright</span>00011 <span class="comment"> * notice remains intact.</span>00012 <span class="comment"> *</span>00013 <span class="comment"> *****************************************************************************/</span>00014 <span class="preprocessor">#ifndef INC_LPC_UART_H</span>00015 <span class="preprocessor"></span><span class="preprocessor">#define INC_LPC_UART_H</span>00016 <span class="preprocessor"></span>00017 <span class="comment">// Universal Asynchronous Receiver Transmitter Registers</span>00018 <span class="keyword">typedef</span> <span class="keyword">struct</span>00019 <span class="keyword"></span>{00020 <span class="keyword">union</span>00021 <span class="keyword"> </span>{00022 REG_8 rbr; <span class="comment">// Receive Buffer Register</span>00023 REG_8 thr; <span class="comment">// Transmit Holding Register</span>00024 REG_8 dll; <span class="comment">// Divisor Latch Register (LSB)</span>00025 REG_8 _pad0[4];00026 };00027 00028 <span class="keyword">union</span>00029 <span class="keyword"> </span>{00030 REG_8 ier; <span class="comment">// Interrupt Enable Register</span>00031 REG_8 dlm; <span class="comment">// Divisor Latch Register (MSB)</span>00032 REG_8 _pad1[4];00033 };00034 00035 <span class="keyword">union</span>00036 <span class="keyword"> </span>{00037 REG_8 iir; <span class="comment">// Interrupt ID Register</span>00038 REG_8 fcr; <span class="comment">// FIFO Control Register</span>00039 REG_8 _pad2[4];00040 };00041 00042 REG_8 lcr; <span class="comment">// Line Control Registe</span>00043 REG_8 _pad3[3];00044 REG_8 mcr; <span class="comment">// MODEM Control Register</span>00045 REG_8 _pad4[3];00046 REG_8 lsr; <span class="comment">// Line Status Register</span>00047 REG_8 _pad5[3];00048 REG_8 msr; <span class="comment">// MODEM Status Register</span>00049 REG_8 _pad6[3];00050 REG_8 scr; <span class="comment">// Scratch Pad Register</span>00051 REG_8 _pad7[3];00052 } uartRegs_t;00053 <span class="comment"></span>00054 <span class="comment">///////////////////////////////////////////////////////////////////////////////</span>00055 <span class="comment"></span><span class="comment">// UART defines</span>00056 00057 <span class="comment">// Interrupt Enable Register bit definitions</span>00058 <span class="preprocessor">#define UIER_ERBFI (1 << 0) // Enable Receive Data Available Interrupt</span>00059 <span class="preprocessor"></span><span class="preprocessor">#define UIER_ETBEI (1 << 1) // Enable Transmit Holding Register Empty Interrupt</span>00060 <span class="preprocessor"></span><span class="preprocessor">#define UIER_ELSI (1 << 2) // Enable Receive Line Status Interrupt</span>00061 <span class="preprocessor"></span><span class="preprocessor">#define UIER_EDSSI (1 << 3) // Enable MODEM Status Interrupt</span>00062 <span class="preprocessor"></span>00063 <span class="comment">// Interrupt ID Register bit definitions</span>00064 <span class="preprocessor">#define UIIR_NO_INT (1 << 0) // NO INTERRUPTS PENDING</span>00065 <span class="preprocessor"></span><span class="preprocessor">#define UIIR_MS_INT (0 << 1) // MODEM Status</span>00066 <span class="preprocessor"></span><span class="preprocessor">#define UIIR_THRE_INT (1 << 1) // Transmit Holding Register Empty</span>00067 <span class="preprocessor"></span><span class="preprocessor">#define UIIR_RDA_INT (2 << 1) // Receive Data Available</span>00068 <span class="preprocessor"></span><span class="preprocessor">#define UIIR_RLS_INT (3 << 1) // Receive Line Status</span>00069 <span class="preprocessor"></span><span class="preprocessor">#define UIIR_CTI_INT (6 << 1) // Character Timeout Indicator</span>00070 <span class="preprocessor"></span><span class="preprocessor">#define UIIR_ID_MASK 0x0E</span>00071 <span class="preprocessor"></span>00072 <span class="comment">// FIFO Control Register bit definitions</span>00073 <span class="preprocessor">#define UFCR_FIFO_ENABLE (1 << 0) // FIFO Enable</span>00074 <span class="preprocessor"></span><span class="preprocessor">#define UFCR_RX_FIFO_RESET (1 << 1) // Reset Receive FIFO</span>00075 <span class="preprocessor"></span><span class="preprocessor">#define UFCR_TX_FIFO_RESET (1 << 2) // Reset Transmit FIFO</span>00076 <span class="preprocessor"></span><span class="preprocessor">#define UFCR_FIFO_TRIG1 (0 << 4) // Trigger @ 1 character in FIFO</span>00077 <span class="preprocessor"></span><span class="preprocessor">#define UFCR_FIFO_TRIG4 (1 << 4) // Trigger @ 4 characters in FIFO</span>00078 <span class="preprocessor"></span><span class="preprocessor">#define UFCR_FIFO_TRIG8 (2 << 4) // Trigger @ 8 characters in FIFO</span>00079 <span class="preprocessor"></span><span class="preprocessor">#define UFCR_FIFO_TRIG14 (3 << 4) // Trigger @ 14 characters in FIFO</span>00080 <span class="preprocessor"></span>00081 <span class="comment">// Line Control Register bit definitions</span>00082 <span class="preprocessor">#define ULCR_CHAR_5 (0 << 0) // 5-bit character length</span>00083 <span class="preprocessor"></span><span class="preprocessor">#define ULCR_CHAR_6 (1 << 0) // 6-bit character length</span>00084 <span class="preprocessor"></span><span class="preprocessor">#define ULCR_CHAR_7 (2 << 0) // 7-bit character length</span>00085 <span class="preprocessor"></span><span class="preprocessor">#define ULCR_CHAR_8 (3 << 0) // 8-bit character length</span>00086 <span class="preprocessor"></span><span class="preprocessor">#define ULCR_STOP_0 (0 << 2) // no stop bits</span>00087 <span class="preprocessor"></span><span class="preprocessor">#define ULCR_STOP_1 (1 << 2) // 1 stop bit</span>00088 <span class="preprocessor"></span><span class="preprocessor">#define ULCR_PAR_NO (0 << 3) // No Parity</span>00089 <span class="preprocessor"></span><span class="preprocessor">#define ULCR_PAR_ODD (1 << 3) // Odd Parity</span>00090 <span class="preprocessor"></span><span class="preprocessor">#define ULCR_PAR_EVEN (3 << 3) // Even Parity</span>00091 <span class="preprocessor"></span><span class="preprocessor">#define ULCR_PAR_MARK (5 << 3) // MARK "1" Parity</span>00092 <span class="preprocessor"></span><span class="preprocessor">#define ULCR_PAR_SPACE (7 << 3) // SPACE "0" Paruty</span>00093 <span class="preprocessor"></span><span class="preprocessor">#define ULCR_BREAK_ENABLE (1 << 6) // Output BREAK line condition</span>00094 <span class="preprocessor"></span><span class="preprocessor">#define ULCR_DLAB_ENABLE (1 << 7) // Enable Divisor Latch Access</span>00095 <span class="preprocessor"></span>00096 <span class="comment">// Modem Control Register bit definitions</span>00097 <span class="preprocessor">#define UMCR_DTR (1 << 0) // Data Terminal Ready</span>00098 <span class="preprocessor"></span><span class="preprocessor">#define UMCR_RTS (1 << 1) // Request To Send</span>00099 <span class="preprocessor"></span><span class="preprocessor">#define UMCR_LB (1 << 4) // Loopback</span>00100 <span class="preprocessor"></span>00101 <span class="comment">// Line Status Register bit definitions</span>00102 <span class="preprocessor">#define ULSR_RDR (1 << 0) // Receive Data Ready</span>00103 <span class="preprocessor"></span><span class="preprocessor">#define ULSR_OE (1 << 1) // Overrun Error</span>00104 <span class="preprocessor"></span><span class="preprocessor">#define ULSR_PE (1 << 2) // Parity Error</span>00105 <span class="preprocessor"></span><span class="preprocessor">#define ULSR_FE (1 << 3) // Framing Error</span>00106 <span class="preprocessor"></span><span class="preprocessor">#define ULSR_BI (1 << 4) // Break Interrupt</span>00107 <span class="preprocessor"></span><span class="preprocessor">#define ULSR_THRE (1 << 5) // Transmit Holding Register Empty</span>00108 <span class="preprocessor"></span><span class="preprocessor">#define ULSR_TEMT (1 << 6) // Transmitter Empty</span>00109 <span class="preprocessor"></span><span class="preprocessor">#define ULSR_RXFE (1 << 7) // Error in Receive FIFO</span>00110 <span class="preprocessor"></span><span class="preprocessor">#define ULSR_ERR_MASK 0x1E</span>00111 <span class="preprocessor"></span>00112 <span class="comment">// Modem Status Register bit definitions</span>00113 <span class="preprocessor">#define UMSR_DCTS (1 << 0) // Delta Clear To Send</span>00114 <span class="preprocessor"></span><span class="preprocessor">#define UMSR_DDSR (1 << 1) // Delta Data Set Ready</span>00115 <span class="preprocessor"></span><span class="preprocessor">#define UMSR_TERI (1 << 2) // Trailing Edge Ring Indicator</span>00116 <span class="preprocessor"></span><span class="preprocessor">#define UMSR_DDCD (1 << 3) // Delta Data Carrier Detect</span>00117 <span class="preprocessor"></span><span class="preprocessor">#define UMSR_CTS (1 << 4) // Clear To Send</span>00118 <span class="preprocessor"></span><span class="preprocessor">#define UMSR_DSR (1 << 5) // Data Set Ready</span>00119 <span class="preprocessor"></span><span class="preprocessor">#define UMSR_RI (1 << 6) // Ring Indicator</span>00120 <span class="preprocessor"></span><span class="preprocessor">#define UMSR_DCD (1 << 7) // Data Carrier Detect</span>00121 <span class="preprocessor"></span>00122 <span class="preprocessor">#endif</span></pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue Jul 13 03:38:12 2004 for Procyon ARMlib-LPC2100 by<a href="http://www.doxygen.org/index.html"><img src="doxygen.png" alt="doxygen" align="middle" border=0 > </a>1.3.6 </small></address></body></html>⌨️ 快捷键说明
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