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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"><html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1"><title>Procyon ARMlib-LPC2100: lpcVIC.h Source File</title><link href="dox.css" rel="stylesheet" type="text/css"></head><body><!-- Generated by Doxygen 1.3.6 --><div class="qindex"><a class="qindex" href="main.html">Main Page</a> | <a class="qindex" href="files.html">File List</a> | <a class="qindex" href="globals.html">Globals</a></div><h1>lpcVIC.h</h1><div class="fragment"><pre>00001 <span class="comment">/******************************************************************************</span>00002 <span class="comment"> *</span>00003 <span class="comment"> * $RCSfile: $</span>00004 <span class="comment"> * $Revision: $</span>00005 <span class="comment"> *</span>00006 <span class="comment"> * Header file for Philips LPC ARM Processors.</span>00007 <span class="comment"> * Copyright 2004 R O SoftWare</span>00008 <span class="comment"> *</span>00009 <span class="comment"> * No guarantees, warrantees, or promises, implied or otherwise.</span>00010 <span class="comment"> * May be used for hobby or commercial purposes provided copyright</span>00011 <span class="comment"> * notice remains intact.</span>00012 <span class="comment"> *</span>00013 <span class="comment"> *****************************************************************************/</span>00014 <span class="preprocessor">#ifndef INC_LPC_VIC_H</span>00015 <span class="preprocessor"></span><span class="preprocessor">#define INC_LPC_VIC_H</span>00016 <span class="preprocessor"></span>00017 <span class="comment">// Vectored Interrupt Controller Registers (VIC)</span>00018 <span class="keyword">typedef</span> <span class="keyword">struct</span>00019 <span class="keyword"></span>{00020 REG32 irqStatus; <span class="comment">// IRQ Status Register</span>00021 REG32 fiqStatus; <span class="comment">// FIQ Status Register</span>00022 REG32 rawIntr; <span class="comment">// Raw Interrupt Status Register</span>00023 REG32 intSelect; <span class="comment">// Interrupt Select Register</span>00024 REG32 intEnable; <span class="comment">// Interrupt Enable Register</span>00025 REG32 intEnClear; <span class="comment">// Interrupt Enable Clear Register</span>00026 REG32 softInt; <span class="comment">// Software Interrupt Register</span>00027 REG32 softIntClear; <span class="comment">// Software Interrupt Clear Register</span>00028 REG32 protection; <span class="comment">// Protection Enable Register</span>00029 REG32 _pad0[3];00030 REG32 vectAddr; <span class="comment">// Vector Address Register</span>00031 REG32 defVectAddr; <span class="comment">// Default Vector Address Register</span>00032 REG32 _pad1[50];00033 REG32 vectAddr0; <span class="comment">// Vector Address 0 Register</span>00034 REG32 vectAddr1; <span class="comment">// Vector Address 1 Register</span>00035 REG32 vectAddr2; <span class="comment">// Vector Address 2 Register</span>00036 REG32 vectAddr3; <span class="comment">// Vector Address 3 Register</span>00037 REG32 vectAddr4; <span class="comment">// Vector Address 4 Register</span>00038 REG32 vectAddr5; <span class="comment">// Vector Address 5 Register</span>00039 REG32 vectAddr6; <span class="comment">// Vector Address 6 Register</span>00040 REG32 vectAddr7; <span class="comment">// Vector Address 7 Register</span>00041 REG32 vectAddr8; <span class="comment">// Vector Address 8 Register</span>00042 REG32 vectAddr9; <span class="comment">// Vector Address 9 Register</span>00043 REG32 vectAddr10; <span class="comment">// Vector Address 10 Register</span>00044 REG32 vectAddr11; <span class="comment">// Vector Address 11 Register</span>00045 REG32 vectAddr12; <span class="comment">// Vector Address 12 Register</span>00046 REG32 vectAddr13; <span class="comment">// Vector Address 13 Register</span>00047 REG32 vectAddr14; <span class="comment">// Vector Address 14 Register</span>00048 REG32 vectAddr15; <span class="comment">// Vector Address 15 Register</span>00049 REG32 _pad2[48];00050 REG32 vectCntl0; <span class="comment">// Vector Control 0 Register</span>00051 REG32 vectCntl1; <span class="comment">// Vector Control 1 Register</span>00052 REG32 vectCntl2; <span class="comment">// Vector Control 2 Register</span>00053 REG32 vectCntl3; <span class="comment">// Vector Control 3 Register</span>00054 REG32 vectCntl4; <span class="comment">// Vector Control 4 Register</span>00055 REG32 vectCntl5; <span class="comment">// Vector Control 5 Register</span>00056 REG32 vectCntl6; <span class="comment">// Vector Control 6 Register</span>00057 REG32 vectCntl7; <span class="comment">// Vector Control 7 Register</span>00058 REG32 vectCntl8; <span class="comment">// Vector Control 8 Register</span>00059 REG32 vectCntl9; <span class="comment">// Vector Control 9 Register</span>00060 REG32 vectCntl10; <span class="comment">// Vector Control 10 Register</span>00061 REG32 vectCntl11; <span class="comment">// Vector Control 11 Register</span>00062 REG32 vectCntl12; <span class="comment">// Vector Control 12 Register</span>00063 REG32 vectCntl13; <span class="comment">// Vector Control 13 Register</span>00064 REG32 vectCntl14; <span class="comment">// Vector Control 14 Register</span>00065 REG32 vectCntl15; <span class="comment">// Vector Control 15 Register</span>00066 } vicRegs_t;00067 00068 <span class="comment">// VIC Channel Assignments</span>00069 <span class="preprocessor">#define VIC_WDT 0</span>00070 <span class="preprocessor"></span><span class="preprocessor">#define VIC_TIMER0 4</span>00071 <span class="preprocessor"></span><span class="preprocessor">#define VIC_TIMER1 5</span>00072 <span class="preprocessor"></span><span class="preprocessor">#define VIC_UART0 6</span>00073 <span class="preprocessor"></span><span class="preprocessor">#define VIC_UART1 7</span>00074 <span class="preprocessor"></span><span class="preprocessor">#define VIC_PWM 8</span>00075 <span class="preprocessor"></span><span class="preprocessor">#define VIC_PWM0 8</span>00076 <span class="preprocessor"></span><span class="preprocessor">#define VIC_I2C 9</span>00077 <span class="preprocessor"></span><span class="preprocessor">#define VIC_SPI 10</span>00078 <span class="preprocessor"></span><span class="preprocessor">#define VIC_SPI0 10</span>00079 <span class="preprocessor"></span><span class="preprocessor">#define VIC_SPI1 11</span>00080 <span class="preprocessor"></span><span class="preprocessor">#define VIC_PLL 12</span>00081 <span class="preprocessor"></span><span class="preprocessor">#define VIC_RTC 13</span>00082 <span class="preprocessor"></span><span class="preprocessor">#define VIC_EINT0 14</span>00083 <span class="preprocessor"></span><span class="preprocessor">#define VIC_EINT1 15</span>00084 <span class="preprocessor"></span><span class="preprocessor">#define VIC_EINT2 16</span>00085 <span class="preprocessor"></span><span class="preprocessor">#define VIC_EINT3 17</span>00086 <span class="preprocessor"></span><span class="preprocessor">#define VIC_ADC 18</span>00087 <span class="preprocessor"></span>00088 <span class="comment">// Vector Control Register bit definitions</span>00089 <span class="preprocessor">#define VIC_ENABLE (1 << 5)</span>00090 <span class="preprocessor"></span>00091 <span class="comment">// Convert Channel Number to Bit Value</span>00092 <span class="preprocessor">#define VIC_BIT(chan) (1 << (chan))</span>00093 <span class="preprocessor"></span>00094 <span class="preprocessor">#endif</span>00095 <span class="preprocessor"></span></pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue Jul 13 03:38:12 2004 for Procyon ARMlib-LPC2100 by<a href="http://www.doxygen.org/index.html"><img src="doxygen.png" alt="doxygen" align="middle" border=0 > </a>1.3.6 </small></address></body></html>⌨️ 快捷键说明
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