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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"><html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1"><title>Procyon ARMlib-LPC2100: lpcSCB.h Source File</title><link href="dox.css" rel="stylesheet" type="text/css"></head><body><!-- Generated by Doxygen 1.3.6 --><div class="qindex"><a class="qindex" href="main.html">Main Page</a> | <a class="qindex" href="files.html">File List</a> | <a class="qindex" href="globals.html">Globals</a></div><h1>lpcSCB.h</h1><div class="fragment"><pre>00001 <span class="comment">/******************************************************************************</span>00002 <span class="comment"> *</span>00003 <span class="comment"> * $RCSfile: $</span>00004 <span class="comment"> * $Revision: $</span>00005 <span class="comment"> *</span>00006 <span class="comment"> * Header file for Philips LPC ARM Processors.</span>00007 <span class="comment"> * Copyright 2004 R O SoftWare</span>00008 <span class="comment"> *</span>00009 <span class="comment"> * No guarantees, warrantees, or promises, implied or otherwise.</span>00010 <span class="comment"> * May be used for hobby or commercial purposes provided copyright</span>00011 <span class="comment"> * notice remains intact.</span>00012 <span class="comment"> *</span>00013 <span class="comment"> *****************************************************************************/</span>00014 <span class="preprocessor">#ifndef INC_LPC_SCB_H</span>00015 <span class="preprocessor"></span><span class="preprocessor">#define INC_LPC_SCB_H</span>00016 <span class="preprocessor"></span>00017 <span class="comment">// System Control Block Registers</span>00018 <span class="keyword">typedef</span> <span class="keyword">struct</span>00019 <span class="keyword"></span>{00020 <span class="comment">// Memory Accelerator Module Registers (MAM)</span>00021 <span class="keyword">struct</span>00022 <span class="keyword"> </span>{00023 REG_8 cr; <span class="comment">// Control Register</span>00024 REG_8 _pad0[3];00025 REG_8 tim; <span class="comment">// Timing Control Register</span>00026 REG32 _pad1[14];00027 } mam;00028 00029 <span class="comment">// Memory Mapping Control Register</span>00030 REG_8 memmap;00031 REG32 _pad0[15];00032 00033 <span class="comment">// Phase Locked Loop Registers (PLL)</span>00034 <span class="keyword">struct</span>00035 <span class="keyword"> </span>{00036 REG_8 con; <span class="comment">// Control Register</span>00037 REG_8 _pad0[3];00038 REG_8 cfg; <span class="comment">// Configuration Register</span>00039 REG_8 _pad1[3];00040 REG16 stat; <span class="comment">// Status Register</span>00041 REG16 _pad2;00042 REG_8 feed; <span class="comment">// Feed Register</span>00043 REG32 _pad3[12];00044 } pll;00045 00046 <span class="comment">// Power Control Registers</span>00047 <span class="keyword">struct</span>00048 <span class="keyword"> </span>{00049 REG_8 con; <span class="comment">// Control Register</span>00050 REG_8 _pad0[3];00051 REG32 conp; <span class="comment">// Peripherals Register</span>00052 REG32 _pad1[14];00053 } p;00054 00055 <span class="comment">// VPB Divider Register</span>00056 REG_8 vpbdiv;00057 REG32 _pad1[15];00058 00059 <span class="comment">// External Interrupt Registers</span>00060 <span class="keyword">struct</span>00061 <span class="keyword"> </span>{00062 REG_8 flag; <span class="comment">// Flag Register</span>00063 REG_8 _pad0[3];00064 REG_8 wake; <span class="comment">// Wakeup Register</span>00065 REG_8 _pad1[3];00066 REG_8 mode; <span class="comment">// Mode Register</span>00067 REG_8 _pad2[3];00068 REG_8 polar; <span class="comment">// Polarity Register</span>00069 REG32 _pad3[12];00070 } ext;00071 } scbRegs_t;00072 00073 <span class="comment"></span>00074 <span class="comment">///////////////////////////////////////////////////////////////////////////////</span>00075 <span class="comment"></span><span class="comment">// MAM defines</span>00076 <span class="preprocessor">#define MAMCR_OFF 0</span>00077 <span class="preprocessor"></span><span class="preprocessor">#define MAMCR_PART 1</span>00078 <span class="preprocessor"></span><span class="preprocessor">#define MAMCR_FULL 2</span>00079 <span class="preprocessor"></span>00080 <span class="preprocessor">#define MAMTIM_CYCLES (((CCLK) + 19999999) / 20000000)</span>00081 <span class="preprocessor"></span><span class="comment"></span>00082 <span class="comment">///////////////////////////////////////////////////////////////////////////////</span>00083 <span class="comment"></span><span class="comment">// MEMMAP defines</span>00084 <span class="preprocessor">#define MEMMAP_BBLK 0 // Interrupt Vectors in Boot Block</span>00085 <span class="preprocessor"></span><span class="preprocessor">#define MEMMAP_FLASH 1 // Interrupt Vectors in Flash</span>00086 <span class="preprocessor"></span><span class="preprocessor">#define MEMMAP_SRAM 2 // Interrupt Vectors in SRAM</span>00087 <span class="preprocessor"></span><span class="comment"></span>00088 <span class="comment">///////////////////////////////////////////////////////////////////////////////</span>00089 <span class="comment"></span><span class="comment">// PLL defines & computations</span>00090 <span class="comment">// Compute the value of PLL_DIV and test range validity</span>00091 <span class="comment">// FOSC & PLL_MUL should be defined in project configuration file (config.h)</span>00092 <span class="preprocessor">#ifndef CCLK</span>00093 <span class="preprocessor"></span><span class="preprocessor">#define CCLK (FOSC * PLL_MUL) // CPU Clock Freq.</span>00094 <span class="preprocessor"></span><span class="preprocessor">#endif</span>00095 <span class="preprocessor"></span>00096 <span class="preprocessor">#define FCCO_MAX (320000000) // Max CC Osc Freq.</span>00097 <span class="preprocessor"></span><span class="preprocessor">#define PLL_DIV (FCCO_MAX / (2 * CCLK)) // PLL Divider</span>00098 <span class="preprocessor"></span><span class="preprocessor">#define FCCO (FOSC * PLL_MUL * 2 * PLL_DIV) // CC Osc. Freq.</span>00099 <span class="preprocessor"></span>00100 <span class="comment">// PLLCON Register Bit Definitions</span>00101 <span class="preprocessor">#define PLLCON_PLLE (1 << 0) // PLL Enable</span>00102 <span class="preprocessor"></span><span class="preprocessor">#define PLLCON_PLLC (1 << 1) // PLL Connect</span>00103 <span class="preprocessor"></span>00104 <span class="comment">// PLLCFG Register Bit Definitions</span>00105 <span class="preprocessor">#define PLLCFG_MSEL ((PLL_MUL - 1) << 0) // PLL Multiplier</span>00106 <span class="preprocessor"></span><span class="preprocessor">#define PLLCFG_PSEL ((PLL_DIV - 1) << 5) // PLL Divider</span>00107 <span class="preprocessor"></span>00108 <span class="comment">// PLLSTAT Register Bit Definitions</span>00109 <span class="preprocessor">#define PLLSTAT_LOCK (1 << 10) // PLL Lock Status Bit</span>00110 <span class="preprocessor"></span><span class="comment"></span>00111 <span class="comment">///////////////////////////////////////////////////////////////////////////////</span>00112 <span class="comment"></span><span class="comment">// VPBDIV defines & computations</span>00113 <span class="preprocessor">#define VPBDIV_VALUE (PBSD & 0x03) // VPBDIV value</span>00114 <span class="preprocessor"></span>00115 <span class="preprocessor">#endif</span></pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue Jul 13 03:38:12 2004 for Procyon ARMlib-LPC2100 by<a href="http://www.doxygen.org/index.html"><img src="doxygen.png" alt="doxygen" align="middle" border=0 > </a>1.3.6 </small></address></body></html>⌨️ 快捷键说明
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