📄 lpc21xx_8h-source.html
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00107 <span class="comment"></span>00108 <span class="comment">///////////////////////////////////////////////////////////////////////////////</span>00109 <span class="comment"></span><span class="comment">// Universal Asynchronous Receiver Transmitter 0 (UART0)</span>00110 <span class="preprocessor">#define UART0 ((uartRegs_t *)0xE000C000)</span>00111 <span class="preprocessor"></span><span class="preprocessor">#define U0_PINSEL (0x00000005) </span><span class="comment">/* PINSEL0 Value for UART0 */</span>00112 <span class="preprocessor">#define U0_PINMASK (0x0000000F) </span><span class="comment">/* PINSEL0 Mask for UART0 */</span>00113 00114 <span class="comment">// UART0 Registers</span>00115 <span class="preprocessor">#define U0RBR UART0->rbr </span><span class="comment">/* Receive Buffer Register */</span>00116 <span class="preprocessor">#define U0THR UART0->thr </span><span class="comment">/* Transmit Holding Register */</span>00117 <span class="preprocessor">#define U0IER UART0->ier </span><span class="comment">/* Interrupt Enable Register */</span>00118 <span class="preprocessor">#define U0IIR UART0->iir </span><span class="comment">/* Interrupt ID Register */</span>00119 <span class="preprocessor">#define U0FCR UART0->fcr </span><span class="comment">/* FIFO Control Register */</span>00120 <span class="preprocessor">#define U0LCR UART0->lcr </span><span class="comment">/* Line Control Register */</span>00121 <span class="preprocessor">#define U0LSR UART0->lsr </span><span class="comment">/* Line Status Register */</span>00122 <span class="preprocessor">#define U0SCR UART0->scr </span><span class="comment">/* Scratch Pad Register */</span>00123 <span class="preprocessor">#define U0DLL UART0->dll </span><span class="comment">/* Divisor Latch Register (LSB) */</span>00124 <span class="preprocessor">#define U0DLM UART0->dlm </span><span class="comment">/* Divisor Latch Register (MSB) */</span>00125 <span class="comment"></span>00126 <span class="comment">///////////////////////////////////////////////////////////////////////////////</span>00127 <span class="comment"></span><span class="comment">// Universal Asynchronous Receiver Transmitter 1 (UART1)</span>00128 <span class="preprocessor">#define UART1 ((uartRegs_t *)0xE0010000)</span>00129 <span class="preprocessor"></span><span class="preprocessor">#define U1_PINSEL (0x00050000) </span><span class="comment">/* PINSEL0 Value for UART1 */</span>00130 <span class="preprocessor">#define U1_PINMASK (0x000F0000) </span><span class="comment">/* PINSEL0 Mask for UART1 */</span>00131 00132 <span class="comment">// UART1 Registers</span>00133 <span class="preprocessor">#define U1RBR UART1->rbr </span><span class="comment">/* Receive Buffer Register */</span>00134 <span class="preprocessor">#define U1THR UART1->thr </span><span class="comment">/* Transmit Holding Register */</span>00135 <span class="preprocessor">#define U1IER UART1->ier </span><span class="comment">/* Interrupt Enable Register */</span>00136 <span class="preprocessor">#define U1IIR UART1->iir </span><span class="comment">/* Interrupt ID Register */</span>00137 <span class="preprocessor">#define U1FCR UART1->fcr </span><span class="comment">/* FIFO Control Register */</span>00138 <span class="preprocessor">#define U1LCR UART1->lcr </span><span class="comment">/* Line Control Register */</span>00139 <span class="preprocessor">#define U1MCR UART1->mcr </span><span class="comment">/* MODEM Control Register */</span>00140 <span class="preprocessor">#define U1LSR UART1->lsr </span><span class="comment">/* Line Status Register */</span>00141 <span class="preprocessor">#define U1MSR UART1->msr </span><span class="comment">/* MODEM Status Register */</span>00142 <span class="preprocessor">#define U1SCR UART1->scr </span><span class="comment">/* Scratch Pad Register */</span>00143 <span class="preprocessor">#define U1DLL UART1->dll </span><span class="comment">/* Divisor Latch Register (LSB) */</span>00144 <span class="preprocessor">#define U1DLM UART1->dlm </span><span class="comment">/* Divisor Latch Register (MSB) */</span>00145 <span class="comment"></span>00146 <span class="comment">///////////////////////////////////////////////////////////////////////////////</span>00147 <span class="comment"></span><span class="comment">// I2C Interface</span>00148 <span class="preprocessor">#define I2C ((i2cRegs_t *)0xE001C000)</span>00149 <span class="preprocessor"></span>00150 <span class="comment">// I2C Registers</span>00151 <span class="preprocessor">#define I2CONSET I2C->conset </span><span class="comment">/* Control Set Register */</span>00152 <span class="preprocessor">#define I2STAT I2C->stat </span><span class="comment">/* Status Register */</span>00153 <span class="preprocessor">#define I2DAT I2C->dat </span><span class="comment">/* Data Register */</span>00154 <span class="preprocessor">#define I2ADR I2C->adr </span><span class="comment">/* Slave Address Register */</span>00155 <span class="preprocessor">#define I2SCLH I2C->sclh </span><span class="comment">/* SCL Duty Cycle Register (high half word) */</span>00156 <span class="preprocessor">#define I2SCLL I2C->scll </span><span class="comment">/* SCL Duty Cycle Register (low half word) */</span>00157 <span class="preprocessor">#define I2CONCLR I2C->conclr </span><span class="comment">/* Control Clear Register */</span>00158 <span class="comment"></span>00159 <span class="comment">///////////////////////////////////////////////////////////////////////////////</span>00160 <span class="comment"></span><span class="comment">// Serial Peripheral Interface 0 (SPI0)</span>00161 <span class="preprocessor">#define SPI0 ((spiRegs_t *)0xE0020000)</span>00162 <span class="preprocessor"></span>00163 <span class="comment">// SPI0 Registers</span>00164 <span class="preprocessor">#define S0SPCR SPI0->cr </span><span class="comment">/* Control Register */</span>00165 <span class="preprocessor">#define S0SPSR SPI0->sr </span><span class="comment">/* Status Register */</span>00166 <span class="preprocessor">#define S0SPDR SPI0->dr </span><span class="comment">/* Data Register */</span>00167 <span class="preprocessor">#define S0SPCCR SPI0->ccr </span><span class="comment">/* Clock Counter Register */</span>00168 <span class="preprocessor">#define S0SPINT SPI0->flag </span><span class="comment">/* Interrupt Flag Register */</span>00169 <span class="comment"></span>00170 <span class="comment">///////////////////////////////////////////////////////////////////////////////</span>00171 <span class="comment"></span><span class="comment">// Serial Peripheral Interface 1 (SPI1)</span>00172 <span class="preprocessor">#define SPI1 ((spiRegs_t *)0xE0030000)</span>00173 <span class="preprocessor"></span>00174 <span class="comment">// SPI1 Registers</span>00175 <span class="preprocessor">#define S1SPCR SPI1->cr </span><span class="comment">/* Control Register */</span>00176 <span class="preprocessor">#define S1SPSR SPI1->sr </span><span class="comment">/* Status Register */</span>00177 <span class="preprocessor">#define S1SPDR SPI1->dr </span><span class="comment">/* Data Register */</span>00178 <span class="preprocessor">#define S1SPCCR SPI1->ccr </span><span class="comment">/* Clock Counter Register */</span>00179 <span class="preprocessor">#define S1SPINT SPI1->flag </span><span class="comment">/* Interrupt Flag Register */</span>00180 <span class="comment"></span>00181 <span class="comment">///////////////////////////////////////////////////////////////////////////////</span>00182 <span class="comment"></span><span class="comment">// Real Time Clock</span>00183 <span class="preprocessor">#define RTC ((rtcRegs_t *)0xE0024000)</span>00184 <span class="preprocessor"></span>00185 <span class="comment">// RTC Registers</span>00186 <span class="preprocessor">#define RTCILR RTC->ilr </span><span class="comment">/* Interrupt Location Register */</span>00187 <span class="preprocessor">#define RTCCTC RTC->ctc </span><span class="comment">/* Clock Tick Counter */</span>00188 <span class="preprocessor">#define RTCCCR RTC->ccr </span><span class="comment">/* Clock Control Register */</span>00189 <span class="preprocessor">#define RTCCIIR RTC->ciir </span><span class="comment">/* Counter Increment Interrupt Register */</span>00190 <span class="preprocessor">#define RTCAMR RTC->amr </span><span class="comment">/* Alarm Mask Register */</span>00191 <span class="preprocessor">#define RTCCTIME0 RTC->ctime0 </span><span class="comment">/* Consolidated Time Register 0 */</span>00192 <span class="preprocessor">#define RTCCTIME1 RTC->ctime1 </span><span class="comment">/* Consolidated Time Register 1 */</span>00193 <span class="preprocessor">#define RTCCTIME2 RTC->ctime2 </span><span class="comment">/* Consolidated Time Register 2 */</span>00194 <span class="preprocessor">#define RTCSEC RTC->sec </span><span class="comment">/* Seconds Register */</span>00195 <span class="preprocessor">#define RTCMIN RTC->min </span><span class="comment">/* Minutes Register */</span>00196 <span class="preprocessor">#define RTCHOUR RTC->hour </span><span class="comment">/* Hours Register */</span>00197 <span class="preprocessor">#define RTCDOM RTC->dom </span><span class="comment">/* Day Of Month Register */</span>00198 <span class="preprocessor">#define RTCDOW RTC->dow </span><span class="comment">/* Day Of Week Register */</span>00199 <span class="preprocessor">#define RTCDOY RTC->doy </span><span class="comment">/* Day Of Year Register */</span>00200 <span class="preprocessor">#define RTCMONTH RTC->month </span><span class="comment">/* Months Register */</span>00201 <span class="preprocessor">#define RTCYEAR RTC->year </span><span class="comment">/* Years Register */</span>00202 <span class="preprocessor">#define RTCALSEC RTC->alsec </span><span class="comment">/* Alarm Seconds Register */</span>00203 <span class="preprocessor">#define RTCALMIN RTC->almin </span><span class="comment">/* Alarm Minutes Register */</span>00204 <span class="preprocessor">#define RTCALHOUR RTC->alhour </span><span class="comment">/* Alarm Hours Register */</span>00205 <span class="preprocessor">#define RTCALDOM RTC->aldom </span><span class="comment">/* Alarm Day Of Month Register */</span>00206 <span class="preprocessor">#define RTCALDOW RTC->aldow </span><span class="comment">/* Alarm Day Of Week Register */</span>00207 <span class="preprocessor">#define RTCALDOY RTC->aldoy </span><span class="comment">/* Alarm Day Of Year Register */</span>00208 <span class="preprocessor">#define RTCALMON RTC->almon </span><span class="comment">/* Alarm Months Register */</span>00209 <span class="preprocessor">#define RTCALYEAR RTC->alyear </span><span class="comment">/* Alarm Years Register */</span>00210 <span class="preprocessor">#define RTCPREINT RTC->preint </span><span class="comment">/* Prescale Value Register (integer) */</span>00211 <span class="preprocessor">#define RTCPREFRAC RTC->prefrac </span><span class="comment">/* Prescale Value Register (fraction) */</span>00212 <span class="comment"></span>00213 <span class="comment">///////////////////////////////////////////////////////////////////////////////</span>00214 <span class="comment"></span><span class="comment">// General Purpose Input/Output</span>00215 <span class="preprocessor">#define GPIO ((gpioRegs_t *)0xE0028000)</span>00216 <span class="preprocessor"></span>00217 <span class="comment">// GPIO Registers</span>00218 <span class="preprocessor">#define IO0PIN GPIO->in0 </span><span class="comment">/* P0 Pin Value Register */</span>00219 <span class="preprocessor">#define IO0SET GPIO->set0 </span><span class="comment">/* P0 Pin Output Set Register */</span>
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