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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"><html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1"><title>Procyon ARMlib-LPC2100: lpcTMR.h Source File</title><link href="dox.css" rel="stylesheet" type="text/css"></head><body><!-- Generated by Doxygen 1.3.6 --><div class="qindex"><a class="qindex" href="main.html">Main Page</a> | <a class="qindex" href="files.html">File List</a> | <a class="qindex" href="globals.html">Globals</a></div><h1>lpcTMR.h</h1><div class="fragment"><pre>00001 <span class="comment">/******************************************************************************</span>00002 <span class="comment"> *</span>00003 <span class="comment"> * $RCSfile: $</span>00004 <span class="comment"> * $Revision: $</span>00005 <span class="comment"> *</span>00006 <span class="comment"> * Header file for Philips LPC ARM Processors.</span>00007 <span class="comment"> * Copyright 2004 R O SoftWare</span>00008 <span class="comment"> *</span>00009 <span class="comment"> * No guarantees, warrantees, or promises, implied or otherwise.</span>00010 <span class="comment"> * May be used for hobby or commercial purposes provided copyright</span>00011 <span class="comment"> * notice remains intact.</span>00012 <span class="comment"> *</span>00013 <span class="comment"> *****************************************************************************/</span>00014 <span class="preprocessor">#ifndef INC_LPC_TMR_H</span>00015 <span class="preprocessor"></span><span class="preprocessor">#define INC_LPC_TMR_H</span>00016 <span class="preprocessor"></span>00017 <span class="comment">// Timer & PWM Registers</span>00018 <span class="keyword">typedef</span> <span class="keyword">struct</span>00019 <span class="keyword"></span>{00020 REG32 ir; <span class="comment">// Interrupt Register</span>00021 REG32 tcr; <span class="comment">// Timer Control Register</span>00022 REG32 tc; <span class="comment">// Timer Counter</span>00023 REG32 pr; <span class="comment">// Prescale Register</span>00024 REG32 pc; <span class="comment">// Prescale Counter Register</span>00025 REG32 mcr; <span class="comment">// Match Control Register</span>00026 REG32 mr0; <span class="comment">// Match Register 0</span>00027 REG32 mr1; <span class="comment">// Match Register 1</span>00028 REG32 mr2; <span class="comment">// Match Register 2</span>00029 REG32 mr3; <span class="comment">// Match Register 3</span>00030 REG32 ccr; <span class="comment">// Capture Control Register</span>00031 REG32 cr0; <span class="comment">// Capture Register 0</span>00032 REG32 cr1; <span class="comment">// Capture Register 1</span>00033 REG32 cr2; <span class="comment">// Capture Register 2</span>00034 REG32 cr3; <span class="comment">// Capture Register 3</span>00035 REG32 emr; <span class="comment">// External Match Register</span>00036 REG32 mr4; <span class="comment">// Match Register 4</span>00037 REG32 mr5; <span class="comment">// Match Register 5</span>00038 REG32 mr6; <span class="comment">// Match Register 6</span>00039 REG32 pcr; <span class="comment">// Control Register</span>00040 REG32 ler; <span class="comment">// Latch Enable Register</span>00041 } pwmTmrRegs_t;00042 00043 <span class="comment">// Timer Interrupt Register Bit Definitions</span>00044 <span class="preprocessor">#define TIR_MR0I (1 << 0) // Interrupt flag for match channel 0</span>00045 <span class="preprocessor"></span><span class="preprocessor">#define TIR_MR1I (1 << 1) // Interrupt flag for match channel 1</span>00046 <span class="preprocessor"></span><span class="preprocessor">#define TIR_MR2I (1 << 2) // Interrupt flag for match channel 2</span>00047 <span class="preprocessor"></span><span class="preprocessor">#define TIR_MR3I (1 << 3) // Interrupt flag for match channel 3</span>00048 <span class="preprocessor"></span><span class="preprocessor">#define TIR_CR0I (1 << 4) // Interrupt flag for capture channel 0 event</span>00049 <span class="preprocessor"></span><span class="preprocessor">#define TIR_CR1I (1 << 5) // Interrupt flag for capture channel 1 event</span>00050 <span class="preprocessor"></span><span class="preprocessor">#define TIR_CR2I (1 << 6) // Interrupt flag for capture channel 2 event</span>00051 <span class="preprocessor"></span><span class="preprocessor">#define TIR_CR3I (1 << 7) // Interrupt flag for capture channel 3 event</span>00052 <span class="preprocessor"></span>00053 <span class="comment">// PWM Interrupt Register Bit Definitions</span>00054 <span class="preprocessor">#define PWMIR_MR0I (1 << 0) // Interrupt flag for match channel 0</span>00055 <span class="preprocessor"></span><span class="preprocessor">#define PWMIR_MR1I (1 << 1) // Interrupt flag for match channel 1</span>00056 <span class="preprocessor"></span><span class="preprocessor">#define PWMIR_MR2I (1 << 2) // Interrupt flag for match channel 2</span>00057 <span class="preprocessor"></span><span class="preprocessor">#define PWMIR_MR3I (1 << 3) // Interrupt flag for match channel 3</span>00058 <span class="preprocessor"></span><span class="preprocessor">#define PWMIR_MR4I (1 << 8) // Interrupt flag for match channel 4</span>00059 <span class="preprocessor"></span><span class="preprocessor">#define PWMIR_MR5I (1 << 9) // Interrupt flag for match channel 5</span>00060 <span class="preprocessor"></span><span class="preprocessor">#define PWMIR_MR6I (1 << 10) // Interrupt flag for match channel 6</span>00061 <span class="preprocessor"></span><span class="preprocessor">#define PWMIR_MASK (0x070F)</span>00062 <span class="preprocessor"></span>00063 <span class="comment">// Timer Control Register Bit Definitions</span>00064 <span class="preprocessor">#define TCR_ENABLE (1 << 0)</span>00065 <span class="preprocessor"></span><span class="preprocessor">#define TCR_RESET (1 << 1)</span>00066 <span class="preprocessor"></span>00067 <span class="comment">// PWM Control Register Bit Definitions</span>00068 <span class="preprocessor">#define PWMCR_ENABLE (1 << 0)</span>00069 <span class="preprocessor"></span><span class="preprocessor">#define PWMCR_RESET (1 << 1)</span>00070 <span class="preprocessor"></span>00071 <span class="comment">// Timer Match Control Register Bit Definitions</span>00072 <span class="preprocessor">#define TMCR_MR0_I (1 << 0) // Enable Interrupt when MR0 matches TC</span>00073 <span class="preprocessor"></span><span class="preprocessor">#define TMCR_MR0_R (1 << 1) // Enable Reset of TC upon MR0 match</span>00074 <span class="preprocessor"></span><span class="preprocessor">#define TMCR_MR0_S (1 << 2) // Enable Stop of TC upon MR0 match</span>00075 <span class="preprocessor"></span><span class="preprocessor">#define TMCR_MR1_I (1 << 3) // Enable Interrupt when MR1 matches TC</span>00076 <span class="preprocessor"></span><span class="preprocessor">#define TMCR_MR1_R (1 << 4) // Enable Reset of TC upon MR1 match</span>00077 <span class="preprocessor"></span><span class="preprocessor">#define TMCR_MR1_S (1 << 5) // Enable Stop of TC upon MR1 match</span>00078 <span class="preprocessor"></span><span class="preprocessor">#define TMCR_MR2_I (1 << 6) // Enable Interrupt when MR2 matches TC</span>00079 <span class="preprocessor"></span><span class="preprocessor">#define TMCR_MR2_R (1 << 7) // Enable Reset of TC upon MR2 match</span>00080 <span class="preprocessor"></span><span class="preprocessor">#define TMCR_MR2_S (1 << 8) // Enable Stop of TC upon MR2 match</span>00081 <span class="preprocessor"></span><span class="preprocessor">#define TMCR_MR3_I (1 << 9) // Enable Interrupt when MR3 matches TC</span>00082 <span class="preprocessor"></span><span class="preprocessor">#define TMCR_MR3_R (1 << 10) // Enable Reset of TC upon MR3 match</span>00083 <span class="preprocessor"></span><span class="preprocessor">#define TMCR_MR3_S (1 << 11) // Enable Stop of TC upon MR3 match</span>00084 <span class="preprocessor"></span>00085 <span class="comment">// Timer Capture Control Register Bit Definitions</span>00086 <span class="preprocessor">#define TCCR_CR0_R (1 << 0) // Enable Rising edge on CAPn.0 will load TC to CR0</span>00087 <span class="preprocessor"></span><span class="preprocessor">#define TCCR_CR0_F (1 << 1) // Enable Falling edge on CAPn.0 will load TC to CR0</span>00088 <span class="preprocessor"></span><span class="preprocessor">#define TCCR_CR0_I (1 << 2) // Enable Interrupt on load of CR0</span>00089 <span class="preprocessor"></span><span class="preprocessor">#define TCCR_CR1_R (1 << 3) // Enable Rising edge on CAPn.1 will load TC to CR1</span>00090 <span class="preprocessor"></span><span class="preprocessor">#define TCCR_CR1_F (1 << 4) // Enable Falling edge on CAPn.1 will load TC to CR1</span>00091 <span class="preprocessor"></span><span class="preprocessor">#define TCCR_CR1_I (1 << 5) // Enable Interrupt on load of CR1</span>00092 <span class="preprocessor"></span><span class="preprocessor">#define TCCR_CR2_R (1 << 6) // Enable Rising edge on CAPn.2 will load TC to CR2</span>00093 <span class="preprocessor"></span><span class="preprocessor">#define TCCR_CR2_F (1 << 7) // Enable Falling edge on CAPn.2 will load TC to CR2</span>00094 <span class="preprocessor"></span><span class="preprocessor">#define TCCR_CR2_I (1 << 8) // Enable Interrupt on load of CR2</span>00095 <span class="preprocessor"></span><span class="preprocessor">#define TCCR_CR3_R (1 << 9) // Enable Rising edge on CAPn.3 will load TC to CR3</span>00096 <span class="preprocessor"></span><span class="preprocessor">#define TCCR_CR3_F (1 << 10) // Enable Falling edge on CAPn.3 will load TC to CR3</span>00097 <span class="preprocessor"></span><span class="preprocessor">#define TCCR_CR3_I (1 << 11) // Enable Interrupt on load of CR3</span>00098 <span class="preprocessor"></span>00099 <span class="preprocessor">#endif</span></pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue Jul 13 03:38:12 2004 for Procyon ARMlib-LPC2100 by<a href="http://www.doxygen.org/index.html"><img src="doxygen.png" alt="doxygen" align="middle" border=0 > </a>1.3.6 </small></address></body></html>⌨️ 快捷键说明
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