lpc210x_8h-source.html

方便飞利浦arm7tdmi 处理器lpc2100开发的C函数库 Procyon ARMlib-LPC2100 C-Language Function Library for Philips LPC21

00202 <span class="comment"></span><span class="comment">// General Purpose Input/Output</span>
00203 <span class="preprocessor">#define GPIO            ((gpioRegs_t *)0xE0028000)</span>
00204 <span class="preprocessor"></span>
00205 <span class="comment">// GPIO Registers</span>
00206 <span class="preprocessor">#define IOPIN           GPIO-&gt;in0       </span><span class="comment">/* Pin Value Register */</span>
00207 <span class="preprocessor">#define IOSET           GPIO-&gt;set0      </span><span class="comment">/* Pin Output Set Register */</span>
00208 <span class="preprocessor">#define IODIR           GPIO-&gt;dir0      </span><span class="comment">/* Pin Direction Register */</span>
00209 <span class="preprocessor">#define IOCLR           GPIO-&gt;clr0      </span><span class="comment">/* Pin Output Clear Register */</span>
00210 <span class="comment"></span>
00211 <span class="comment">///////////////////////////////////////////////////////////////////////////////</span>
00212 <span class="comment"></span><span class="comment">// Pin Connect Block</span>
00213 <span class="preprocessor">#define PINSEL          ((pinRegs_t *)0xE002C000)</span>
00214 <span class="preprocessor"></span>
00215 <span class="comment">// Pin Connect Block Registers</span>
00216 <span class="preprocessor">#define PINSEL0         PINSEL-&gt;sel0    </span><span class="comment">/* Pin Function Select Register 0 */</span>
00217 <span class="preprocessor">#define PINSEL1         PINSEL-&gt;sel1    </span><span class="comment">/* Pin Function Select Register 1 */</span>
00218 <span class="comment"></span>
00219 <span class="comment">///////////////////////////////////////////////////////////////////////////////</span>
00220 <span class="comment"></span><span class="comment">// System Contol Block</span>
00221 <span class="preprocessor">#define SCB             ((scbRegs_t *)0xE01FC000)</span>
00222 <span class="preprocessor"></span>
00223 <span class="comment">// Memory Accelerator Module Registers (MAM)</span>
00224 <span class="preprocessor">#define MAMCR           SCB-&gt;mam.cr     </span><span class="comment">/* Control Register */</span>
00225 <span class="preprocessor">#define MAMTIM          SCB-&gt;mam.tim    </span><span class="comment">/* Timing Control Register */</span>
00226 
00227 <span class="comment">// Memory Mapping Control Register</span>
00228 <span class="preprocessor">#define MEMMAP          SCB-&gt;memmap</span>
00229 <span class="preprocessor"></span>
00230 <span class="comment">// Phase Locked Loop Registers (PLL)</span>
00231 <span class="preprocessor">#define PLLCON          SCB-&gt;pll.con    </span><span class="comment">/* Control Register */</span>
00232 <span class="preprocessor">#define PLLCFG          SCB-&gt;pll.cfg    </span><span class="comment">/* Configuration Register */</span>
00233 <span class="preprocessor">#define PLLSTAT         SCB-&gt;pll.stat   </span><span class="comment">/* Status Register */</span>
00234 <span class="preprocessor">#define PLLFEED         SCB-&gt;pll.feed   </span><span class="comment">/* Feed Register */</span>
00235 
00236 <span class="comment">// Power Control Registers</span>
00237 <span class="preprocessor">#define PCON            SCB-&gt;p.con      </span><span class="comment">/* Control Register */</span>
00238 <span class="preprocessor">#define PCONP           SCB-&gt;p.conp     </span><span class="comment">/* Peripherals Register */</span>
00239 
00240 <span class="comment">// VPB Divider Register</span>
00241 <span class="preprocessor">#define VPBDIV          SCB-&gt;vpbdiv</span>
00242 <span class="preprocessor"></span>
00243 <span class="comment">// External Interrupt Registers</span>
00244 <span class="preprocessor">#define EXTINT          SCB-&gt;ext.flag   </span><span class="comment">/* Flag Register */</span>
00245 <span class="preprocessor">#define EXTWAKE         SCB-&gt;ext.wake   </span><span class="comment">/* Wakeup Register */</span>
00246 <span class="comment"></span>
00247 <span class="comment">///////////////////////////////////////////////////////////////////////////////</span>
00248 <span class="comment"></span><span class="comment">// Vectored Interrupt Controller</span>
00249 <span class="preprocessor">#define VIC             ((vicRegs_t *)0xFFFFF000)</span>
00250 <span class="preprocessor"></span>
00251 <span class="comment">// Vectored Interrupt Controller Registers</span>
00252 <span class="preprocessor">#define VICIRQStatus    VIC-&gt;irqStatus  </span><span class="comment">/* IRQ Status Register */</span>
00253 <span class="preprocessor">#define VICFIQStatus    VIC-&gt;fiqStatus  </span><span class="comment">/* FIQ Status Register */</span>
00254 <span class="preprocessor">#define VICRawIntr      VIC-&gt;rawIntr    </span><span class="comment">/* Raw Interrupt Status Register */</span>
00255 <span class="preprocessor">#define VICIntSelect    VIC-&gt;intSelect  </span><span class="comment">/* Interrupt Select Register */</span>
00256 <span class="preprocessor">#define VICIntEnable    VIC-&gt;intEnable  </span><span class="comment">/* Interrupt Enable Register */</span>
00257 <span class="preprocessor">#define VICIntEnClear   VIC-&gt;intEnClear </span><span class="comment">/* Interrupt Enable Clear Register */</span>
00258 <span class="preprocessor">#define VICSoftInt      VIC-&gt;softInt    </span><span class="comment">/* Software Interrupt Register */</span>
00259 <span class="preprocessor">#define VICSoftIntClear VIC-&gt;softIntClear </span><span class="comment">/* Software Interrupt Clear Register */</span>
00260 <span class="preprocessor">#define VICProtection   VIC-&gt;protection </span><span class="comment">/* Protection Enable Register */</span>
00261 <span class="preprocessor">#define VICVectAddr     VIC-&gt;vectAddr   </span><span class="comment">/* Vector Address Register */</span>
00262 <span class="preprocessor">#define VICDefVectAddr  VIC-&gt;defVectAddr </span><span class="comment">/* Default Vector Address Register */</span>
00263 <span class="preprocessor">#define VICVectAddr0    VIC-&gt;vectAddr0  </span><span class="comment">/* Vector Address 0 Register */</span>
00264 <span class="preprocessor">#define VICVectAddr1    VIC-&gt;vectAddr1  </span><span class="comment">/* Vector Address 1 Register */</span>
00265 <span class="preprocessor">#define VICVectAddr2    VIC-&gt;vectAddr2  </span><span class="comment">/* Vector Address 2 Register */</span>
00266 <span class="preprocessor">#define VICVectAddr3    VIC-&gt;vectAddr3  </span><span class="comment">/* Vector Address 3 Register */</span>
00267 <span class="preprocessor">#define VICVectAddr4    VIC-&gt;vectAddr4  </span><span class="comment">/* Vector Address 4 Register */</span>
00268 <span class="preprocessor">#define VICVectAddr5    VIC-&gt;vectAddr5  </span><span class="comment">/* Vector Address 5 Register */</span>
00269 <span class="preprocessor">#define VICVectAddr6    VIC-&gt;vectAddr6  </span><span class="comment">/* Vector Address 6 Register */</span>
00270 <span class="preprocessor">#define VICVectAddr7    VIC-&gt;vectAddr7  </span><span class="comment">/* Vector Address 7 Register */</span>
00271 <span class="preprocessor">#define VICVectAddr8    VIC-&gt;vectAddr8  </span><span class="comment">/* Vector Address 8 Register */</span>
00272 <span class="preprocessor">#define VICVectAddr9    VIC-&gt;vectAddr9  </span><span class="comment">/* Vector Address 9 Register */</span>
00273 <span class="preprocessor">#define VICVectAddr10   VIC-&gt;vectAddr10 </span><span class="comment">/* Vector Address 10 Register */</span>
00274 <span class="preprocessor">#define VICVectAddr11   VIC-&gt;vectAddr11 </span><span class="comment">/* Vector Address 11 Register */</span>
00275 <span class="preprocessor">#define VICVectAddr12   VIC-&gt;vectAddr12 </span><span class="comment">/* Vector Address 12 Register */</span>
00276 <span class="preprocessor">#define VICVectAddr13   VIC-&gt;vectAddr13 </span><span class="comment">/* Vector Address 13 Register */</span>
00277 <span class="preprocessor">#define VICVectAddr14   VIC-&gt;vectAddr14 </span><span class="comment">/* Vector Address 14 Register */</span>
00278 <span class="preprocessor">#define VICVectAddr15   VIC-&gt;vectAddr15 </span><span class="comment">/* Vector Address 15 Register */</span>
00279 <span class="preprocessor">#define VICVectCntl0    VIC-&gt;vectCntl0  </span><span class="comment">/* Vector Control 0 Register */</span>
00280 <span class="preprocessor">#define VICVectCntl1    VIC-&gt;vectCntl1  </span><span class="comment">/* Vector Control 1 Register */</span>
00281 <span class="preprocessor">#define VICVectCntl2    VIC-&gt;vectCntl2  </span><span class="comment">/* Vector Control 2 Register */</span>
00282 <span class="preprocessor">#define VICVectCntl3    VIC-&gt;vectCntl3  </span><span class="comment">/* Vector Control 3 Register */</span>
00283 <span class="preprocessor">#define VICVectCntl4    VIC-&gt;vectCntl4  </span><span class="comment">/* Vector Control 4 Register */</span>
00284 <span class="preprocessor">#define VICVectCntl5    VIC-&gt;vectCntl5  </span><span class="comment">/* Vector Control 5 Register */</span>
00285 <span class="preprocessor">#define VICVectCntl6    VIC-&gt;vectCntl6  </span><span class="comment">/* Vector Control 6 Register */</span>
00286 <span class="preprocessor">#define VICVectCntl7    VIC-&gt;vectCntl7  </span><span class="comment">/* Vector Control 7 Register */</span>
00287 <span class="preprocessor">#define VICVectCntl8    VIC-&gt;vectCntl8  </span><span class="comment">/* Vector Control 8 Register */</span>
00288 <span class="preprocessor">#define VICVectCntl9    VIC-&gt;vectCntl9  </span><span class="comment">/* Vector Control 9 Register */</span>
00289 <span class="preprocessor">#define VICVectCntl10   VIC-&gt;vectCntl10 </span><span class="comment">/* Vector Control 10 Register */</span>
00290 <span class="preprocessor">#define VICVectCntl11   VIC-&gt;vectCntl11 </span><span class="comment">/* Vector Control 11 Register */</span>
00291 <span class="preprocessor">#define VICVectCntl12   VIC-&gt;vectCntl12 </span><span class="comment">/* Vector Control 12 Register */</span>
00292 <span class="preprocessor">#define VICVectCntl13   VIC-&gt;vectCntl13 </span><span class="comment">/* Vector Control 13 Register */</span>
00293 <span class="preprocessor">#define VICVectCntl14   VIC-&gt;vectCntl14 </span><span class="comment">/* Vector Control 14 Register */</span>
00294 <span class="preprocessor">#define VICVectCntl15   VIC-&gt;vectCntl15 </span><span class="comment">/* Vector Control 15 Register */</span>
00295 
00296 <span class="preprocessor">#endif</span>
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