📄 discrete cosine transform.txt
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CLR .S2 B_k1c0, 0,15, B_c ; Prolog collapse: 0x10000
|| MV .L1X B_c3c5, A_c3c5 ; Twin constant register
|| STH .D2T1 Av_F5t, *+B_o_ptr [16] ;[29,4] (v)
MV .L1X B15, A15 ; Twin stack pointer
|| MVC .S2X A2, IRP ; Restore IRP
|| STH .D2T1 Av_F2t, *-B_o_ptr [ 8] ;[27,4] (v)
;-
ADD .L1 A_f3, A_f4, A_h0 ;[ 8,1]
|| ADD .S2 B_f2, B_f5, B_h1 ;[ 8,1]
|| SUB .L2 B_f2, B_f5, B_g3 ;[ 9,1]
|| LDW .D2T1 *B15[3], A_o
SUB .L1 A_f3, A_f4, A_q1 ;[ 9,1] q1=g2
|| ADD .L2 B_f1, B_f6t, B_g1 ;[ 9,1]
|| SUB .S2 B_f1, B_f6t, B_h3 ;[ 9,1]
|| SHR .S1 A_f7, 16, A_f7
;-
; =========================== PIPE LOOP KERNEL ============================ ;
h_loop:
[!B_c]STH .D1T2 B_F0t, *+A_io_ptr[ 9] ;[20,1]
|| MPY .M1 A_Q0, A_c3c5, A_c5Q0 ;[20,1]
|| MPYLH .M2 B_S0, B_c3c5, B_c3S0 ;[20,1]
|| ADD .S1X A_c7Q1, B_c1S1, A_F1 ;[20,1]
|| SUB .S2X B_c7S1, A_c1Q1, B_F7 ;[20,1]
|| ADD .L1 A_f0, A_f7, A_g0 ;[10,2]
|| ADD .D2 B_h3, B_g3, B_s0a ;[10,2]
|| SUB .L2 B_h3, B_g3, B_q0a ;[10,2]
;-
h_loop_1:
ADD .L2 B_F7, B_k_rnd, B_F7r ;[21,1]
||[!B_c]STH .D2T1 A_F6t, *+B_io_ptr[22] ;[21,1]
|| SUB .S2 B_g1, B_h1, B_r1 ;[11,2]
|| MPYSU .M2 B_s0a, B_k1c0, B_s0b ;[11,2]
|| MPYSU .M1X B_q0a, A_k1c0, A_q0b ;[11,2]
|| ADD .S1 A_g0, A_h0, A_p0 ;[11,2]
|| SUB .L1 A_g0, A_h0, A_r0 ;[11,2]
|| LDH .D1T2 *-A_io_ptr [ 2], B_f5 ;[ 1,3]
;-
h_loop_2:
SUB .S2X B_c3S0, A_c5Q0, B_F3 ;[22,1]
|| ADD .S1X A_c3Q0, B_c5S0, A_F5 ;[22,1]
|| ADD .L1 A_F1, A_k_rnd, A_F1r ;[22,1]
|| MPYH .M2 B_F7r, B_k1c0, B_F7t ;[22,1]
|| ADD .L2 B_g1, B_h1, B_p1 ;[12,2]
|| MPY .M1 A_r0, A_c2c6, A_c6r0 ;[12,2]
|| LDH .D1T1 *-A_io_ptr [ 4], A_f3 ;[ 2,3]
|| LDH .D2T2 *+B_io_ptr [ 2], B_f2 ;[ 2,3]
;-
h_loop_3:
ADD .S2 B_F3, B_k_rnd, B_F3r ;[23,1]
|| SUB .S1X A_p0, B_p1, A_F4 ;[13,2]
|| ADD .L1 A_q0b, A_k_rnd, A_q0c ;[13,2]
|| ADD .L2 B_s0b, B_k_rnd, B_s0c ;[13,2]
|| MPYLH .M2X B_r1, A_c2c6, B_c2r1 ;[13,2]
|| MPYLH .M1 A_r0, A_c2c6, A_c2r0 ;[13,2]
|| LDH .D2T1 *+B_io_ptr [ 4], A_f4 ;[ 3,3]
|| LDH .D1T2 *-A_io_ptr [ 1], B_f6 ;[ 3,3]
;-
h_loop_4:
ADD .L1 A_F5, A_k_rnd, A_F5r ;[24,1]
|| SHR .S2 B_F3r, 16, B_F3t ;[24,1]
||[ A_o]B .S1 h_loop ;[24,1]
|| ADD .L2X A_p0, B_p1, B_F0 ;[14,2]
|| MPYH .M2 B_s0c, B_k1c0, B_s0 ;[14,2]
|| MPYH .M1 A_q0c, A_k1c0, A_q0 ;[14,2]
|| LDH .D1T1 * A_io_ptr--[ 8], A_f7 ;[ 4,3]
|| LDH .D2T2 *+B_io_ptr [ 1], B_f1 ;[ 4,3]
;-
h_loop_5:
ADD .S2 B_F2, B_k_rnd, B_F2r ;[25,1]
|| MPYH .M1 A_F1r, A_k1c0, A_F1t ;[25,1]
|| ADD .D1 A_F4, 4, A_F4r ;[15,2]
|| SUB .S1X A_c6r0, B_c2r1, A_F6 ;[15,2]
|| SUB .L1 A_f0, A_f7, A_s1 ;[15,2] s1=h2
|| ADD .L2 B_F0, 6, B_F0r ;[15,2]
|| MPY .M2X B_r1, A_c2c6, B_c6r1 ;[15,2]
|| LDH .D2T1 * B_io_ptr--[ 8], A_f0 ;[ 5,3]
;-
h_loop_6:
SHR .S1 A_F5r, 16, A_F5t ;[26,1]
|| SHR .S2 B_F2r, 16, B_F2t ;[26,1]
||[!B_c]STH .D2T2 B_F3t, *+B_io_ptr[27] ;[26,1]
|| SUB .L1 A_q1, A_q0, A_Q0 ;[16,2]
|| ADD .L2X A_s1, B_s0, B_S1 ;[16,2]
|| ADD .D1 A_q1, A_q0, A_Q1 ;[16,2]
|| MPYUS .M2 B_c, 2, B_c ;pro. collapse
|| MPYHL .M1X B_c, A_c2c6, A_c ;pro. collapse
;-
h_loop_7:
[!B_c]STH .D1T1 A_F5t, *+A_io_ptr[22] ;[27,1]
||[!B_c]STH .D2T2 B_F2t, *+B_io_ptr[26] ;[27,1]
|| ADD .L1 A_F6, A_k_rnd, A_F6r ;[17,2]
|| SHR .S2 B_F0r, 3, B_F0t ;[17,2]
|| SHR .S1 A_F4r, 3, A_F4t ;[17,2]
|| SUB .L2X A_s1, B_s0, B_S0 ;[17,2]
|| MPY .M2 B_S1, B_c1c7, B_c7S1 ;[17,2]
|| MPY .M1X A_Q1, B_c1c7, A_c7Q1 ;[17,2]
;-
h_loop_8:
[!A_c]STH .D1T1 A_F1t, *+A_io_ptr[18] ;[28,1]
||[!A_c]STH .D2T2 B_F7t, *+B_io_ptr[31] ;[28,1]
|| SHR .S1 A_F6r, 16, A_F6t ;[18,2]
|| ADD .L2X B_c6r1, A_c2r0, B_F2 ;[18,2]
|| MPYLH .M2 B_S1, B_c1c7, B_c1S1 ;[18,2]
|| MPYLH .M1X A_Q1, B_c1c7, A_c1Q1 ;[18,2]
|| ADD .L1 A_f3, A_f4, A_h0 ;[ 8,3]
|| ADD .S2 B_f2, B_f5, B_h1 ;[ 8,3]
;-
h_loop_9:
[ A_o]SUB .S1 A_o, 1, A_o ;[19,2]
||[!B_c]STH .D1T1 A_F4t, *+A_io_ptr[13] ;[19,2]
|| MPYLH .M1 A_Q0, A_c3c5, A_c3Q0 ;[19,2]
|| MPY .M2 B_S0, B_c3c5, B_c5S0 ;[19,2]
|| SUB .L1 A_f3, A_f4, A_q1 ;[ 9,3] q1=g2
|| ADD .L2 B_f1, B_f6, B_g1 ;[ 9,3]
|| SUB .D2 B_f1, B_f6, B_h3 ;[ 9,3]
|| SUB .S2 B_f2, B_f5, B_g3 ;[ 9,3]
; =========================== PIPE LOOP EPILOG ============================ ;
; EPILOG:
;-
* ========================================================================= *
* Epilog / Final Cleanup Code. *
* *
* This code performs the final stores from the epilog while retoring *
* Save-On-Entry values from the stack. The two processes are heavily *
* interwoven in the interest of speed. For instance, the return addr. *
* is loaded immediately and branched to as soon as it lands in the *
* register file. Meanwhile, the final epilog stores complete as the *
* return-branch is taken. *
* *
* Note that a handful of symbolic names have been reassigned in the *
* epilog to avoid interfering with the values being loaded from the *
* stack. *
* ========================================================================= *
.asg B5, B_F7t
.asg B9, B_F2r
.asg B8, B_F3
.asg B8, B_F3r
.asg A9, A_F5t
MPY .M1 A_Q0, A_c3c5, A_c5Q0
|| MPYLH .M2 B_S0, B_c3c5, B_c3S0
|| ADD .S1X A_c7Q1, B_c1S1, A_F1
|| SUB .S2X B_c7S1, A_c1Q1, B_F7
|| ADD .L2 B_F2, B_k_rnd, B_F2r
|| LDW .D2T1 *+ B15[ 2], A0 ; Load CSR's value
|| LDW .D1T2 *+ A15[ 5], B3 ; Load return address
;-
ADD .L2 B_F7, B_k_rnd, B_F7r
|| ADD .L1 A_F1, A_k_rnd, A_F1r
|| LDW .D2T2 *+ B15[ 8], B11 ; Restore B11
|| LDW .D1T1 *+ A15[13], A13 ; Restore A13
MPYH .M2 B_F7r, B_k1c0, B_F7t
|| MPYH .M1 A_F1r, A_k1c0, A_F1t
|| LDW .D1T2 *+ A15[ 6], B10 ; Restore B10
|| LDW .D2T1 *+ B15[ 7], A10 ; Restore A10
;-
ADD .S1X A_c3Q0, B_c5S0, A_F5
|| SUB .S2X B_c3S0, A_c5Q0, B_F3
|| LDW .D1T2 *+ A15[14], B14 ; Restore B14
|| LDW .D2T1 *+ B15[15], A14 ; Restore A14
ADD .L2 B_F3, B_k_rnd, B_F3r
|| ADD .L1 A_F5, A_k_rnd, A_F5r
|| LDW .D1T2 *+ A15[10], B12 ; Restore B12
|| LDW .D2T1 *+ B15[11], A12 ; Restore A12
;-
B .S2 B3 ; Return to caller
|| LDW .D2T1 *+ B15[12], A11 ; Restore A11
SHR .S2 B_F3r, 16, B_F3t
|| LDW .D2T1 *++B15[16], A15 ; Rst. A15, release stack
|| LDW .D1T2 *+ A15[ 9], B13 ; Restore B13
STH .D1T1 A_F1t, *+A_io_ptr[10]
|| STH .D2T2 B_F7t, *+B_io_ptr[23]
|| SHR .S1 A_F5r, 16, A_F5t
;-
STH .D2T1 A_F6t, *+B_io_ptr[22]
|| STH .D1T2 B_F0t, *+A_io_ptr[ 9]
SHR .S2 B_F2r, 16, B_F2t
|| STH .D2T2 B_F3t, *+B_io_ptr[19]
STH .D1T1 A_F5t, *+A_io_ptr[14]
|| STH .D2T2 B_F2t, *+B_io_ptr[18]
|| MVC .S2X A0, CSR ; Restore CSR
;-
; ===== Interruptibility state restored here =====
; ===== Branch Occurs =====
* ===================================⌨️ 快捷键说明
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