📄 decode.v
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DELAY_JUMP = 1'b1;
end
default : ;
endcase
//-----------
// RTE (002B)
//-----------
else if(INSTR_STATE[5:4] == 2'b10) // 002B (don't care INSTR_STATE[11:6])
case (INSTR_SEQ)
0: begin
EX_RDREG_X = 1'b1;
EX_REGNUM_X = 4'hF;
EX_ALUFUNC = `ALU_INCX4;
EX_WRREG_Z = 1'b1;
EX_REGNUM_Z = 4'hF;
EX_WRMAAD_Z = 0; // MAAD = XBUS
{EX_MA_ISSUE,EX_MA_WR} = 2'b10;
EX_MA_SZ = 2'b10;
WB_RDMADR_W = 1'b1;
ID_INCPC = 1'b1;
end
1: begin
EX_RDREG_X = 1'b1;
EX_REGNUM_X = 4'hF;
EX_ALUFUNC = `ALU_INCX4;
EX_WRREG_Z = 1'b1;
EX_REGNUM_Z = 4'hF;
EX_WRMAAD_Z = 1'b0; // MAAD = XBUS
{EX_MA_ISSUE,EX_MA_WR} = 2'b10;
EX_MA_SZ = 2'b10;
WB_RDMADR_W = 1'b1;
WB_WRSR_W = 1'b1;
end
2: begin
EX_ALUFUNC = `ALU_THRUW;
EX_WRPC_Z = 1'b1;
end
3: begin
ID_IF_ISSUE = 1'b1;
ID_IFADSEL = 1'b1;
ID_IF_JP = 1'b1;
DISPATCH = 1'b1;
DELAY_JUMP = 1'b1;
end
default : ;
endcase
//-------------
// SLEEP (001B)
//-------------
else // 001B
case (INSTR_SEQ)
0: begin
end
1: begin
SLP = 1'b1;
end
2: begin
end
3: begin
ID_INCPC = 1'b1;
ID_IF_ISSUE = 1'b1;
DISPATCH = 1'b1;
end
endcase
end
//------------------------
// MAC.L @Rm+, @Rn+ (0nmF)
//------------------------
4'b11?? : // 0xxC, 0xxD, 0xxE, 0xxF
begin
if (INSTR_STATE[1:0] == 2'b11)
case (INSTR_SEQ)
0: begin
EX_RDREG_X = 1'b1;
EX_REGNUM_X = INSTR_STATE[11:8]; //@Rn+
EX_ALUFUNC = `ALU_INCX4;
EX_WRREG_Z = 1'b1;
EX_REGNUM_Z = INSTR_STATE[11:8]; //@Rn+
EX_WRMAAD_Z = 1'b0; // MAAD = XBUS
{EX_MA_ISSUE,EX_MA_WR} = 2'b10;
EX_MA_SZ = 2'b10;
WB_RDMADR_W = 1'b1;
WB_MACSEL1 = 2'b10; // WBUS -> MACIN1
WB_MULCOM1 = 1'b1;
end
1: begin
WB_MAC_BUSY = 1'b1;
MAC_S_LATCH = 1'b1;
EX_RDREG_X = 1'b1;
EX_REGNUM_X = INSTR_STATE[7:4]; //@Rm+
EX_ALUFUNC = `ALU_INCX4;
EX_WRREG_Z = 1'b1;
EX_REGNUM_Z = INSTR_STATE[7:4]; //@Rm+
EX_WRMAAD_Z = 1'b0; // MAAD = XBUS
{EX_MA_ISSUE,EX_MA_WR} = 2'b10;
EX_MA_SZ = 2'b10;
WB_RDMADR_W = 1'b1;
WB_MACSEL2 = 2'b10; // WBUS -> MACIN2
WB_MULCOM2 = {1'b1, INSTR_STATE[14:12], INSTR_STATE[3:0]};
ID_INCPC = 1'b1;
ID_IF_ISSUE = 1'b1;
DISPATCH = 1'b1;
end
default : ;
endcase
//------------------------------
// MOV.B @(R0, Rm), Rn (0nmC)
// MOV.W @(R0, Rm), Rn (0nmD)
// MOV.L @(R0, Rm), Rn (0nmE)
//------------------------------
else
begin
EX_RDREG_X = 1'b1;
EX_REGNUM_X = INSTR_STATE[7:4]; //Rm
EX_ALUFUNC = `ALU_ADDR0; //@(R0, Rm)
EX_WRMAAD_Z = 1'b1;
{EX_MA_ISSUE,EX_MA_WR} = 2'b10;
EX_MA_SZ = INSTR_STATE[1:0];
WB_RDMADR_W = 1'b1;
WB_WRREG_W = 1'b1;
WB_REGNUM_W = INSTR_STATE[11:8]; //Rn
ID_INCPC = 1'b1;
ID_IF_ISSUE = 1'b1;
DISPATCH = 1'b1;
end
end
//---------------
// Default = NOP
//---------------
default :
begin
ID_INCPC = 1'b1;
ID_IF_ISSUE = 1'b1;
DISPATCH = 1'b1;
end
endcase
//============================================
// Line 1xxx
//============================================
//-----------------------------
// MOV.L Rm, @(disp, Rn) (1nmd)
//-----------------------------
4'b0001 : // 1xxx
begin
EX_RDREG_X = 1'b1;
EX_REGNUM_X = INSTR_STATE[11:8]; //Rn
EX_CONST_ZERO44 = 1'b1;
EX_ALUFUNC = `ALU_ADDCN; //@(disp, Rn)
EX_WRMAAD_Z = 1'b1;
EX_RDREG_Y = 1'b1;
EX_REGNUM_Y = INSTR_STATE[7:4]; //Rm
EX_WRMADW_Y = 1'b1;
{EX_MA_ISSUE,EX_MA_WR} = 2'b11;
EX_MA_SZ = 2'b10;
ID_INCPC = 1'b1;
ID_IF_ISSUE = 1'b1;
DISPATCH = 1'b1;
end
//============================================
// Line 2xxx
//============================================
4'b0010 : // 2xxx
casex (INSTR_STATE[3:0])
//-----------------------------------
// MOV.L/W/B Rm, @Rn (2nm2/2nm1/2nm0)
//-----------------------------------
4'b00?? : // 2xx0, 2xx1, 2xx2 (don't care 2xx3)
begin
EX_RDREG_X = 1'b1;
EX_REGNUM_X = INSTR_STATE[11:8]; //@Rn
EX_RDREG_Y = 1'b1;
EX_REGNUM_Y = INSTR_STATE[7:4]; //Rm
EX_WRMADW_Y = 1'b1;
EX_ALUFUNC = `ALU_THRUX;
EX_WRMAAD_Z = 1'b1;
{EX_MA_ISSUE,EX_MA_WR} = 2'b11;
EX_MA_SZ = INSTR_STATE[1:0];
ID_INCPC = 1'b1;
ID_IF_ISSUE = 1'b1;
DISPATCH = 1'b1;
end
//------------------------------------
// MOV.L/W/B Rm, @-Rn (2nm6/2nm5/2nm4)
// DIV0S (2nm7)
//------------------------------------
4'b01?? : // 2xx4, 2xx5, 2xx6, 2xx7
begin
if (INSTR_STATE[1:0] == 2'b11) // 2xx7
begin
EX_RDREG_X = 1'b1;
EX_REGNUM_X = INSTR_STATE[11:8]; //Rn
EX_RDREG_Y = 1'b1;
EX_REGNUM_Y = INSTR_STATE[7:4]; //Rm
EX_MQT_DV0SET = 1'b1;
ID_INCPC = 1'b1;
ID_IF_ISSUE = 1'b1;
DISPATCH = 1'b1;
end
else // 2xx4, 2xx5, 2xx6
begin
EX_RDREG_X = 1'b1;
EX_REGNUM_X = INSTR_STATE[11:8]; //@Rn
case (INSTR_STATE[1:0])
2'b00 : EX_ALUFUNC = `ALU_DECX;
2'b01 : EX_ALUFUNC = `ALU_DECX2;
2'b10 : EX_ALUFUNC = `ALU_DECX4;
default : EX_ALUFUNC = `ALU_NOP;
endcase
EX_WRREG_Z = 1'b1;
EX_REGNUM_Z = INSTR_STATE[11:8]; // @-Rn
EX_WRMAAD_Z = 1'b1;
EX_RDREG_Y = 1'b1;
EX_REGNUM_Y = INSTR_STATE[7:4]; //Rm
EX_WRMADW_Y = 1'b1;
{EX_MA_ISSUE,EX_MA_WR} = 2'b11;
EX_MA_SZ = INSTR_STATE[1:0];
ID_INCPC = 1'b1;
ID_IF_ISSUE = 1'b1;
DISPATCH = 1'b1;
end
end
//------------------
// TST Rm, Rn (2nm8)
// AND Rm, Rn (2nm9)
// XOR Rm, Rn (2nmA)
// OR Rm, Rn (2nmB)
//------------------
4'b10?? : // 2xx8, 2xx9, 2xxA, 2xxB
begin
EX_RDREG_X = 1'b1;
EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
EX_RDREG_Y = 1'b1;
EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
case (INSTR_STATE[1:0])
2'b00 : {EX_ALUFUNC, EX_WRREG_Z, EX_T_TSTSET} = {`ALU_AND, 1'b0, 1'b1};
2'b01 : {EX_ALUFUNC, EX_WRREG_Z, EX_T_TSTSET} = {`ALU_AND, 1'b1, 1'b0};
2'b10 : {EX_ALUFUNC, EX_WRREG_Z, EX_T_TSTSET} = {`ALU_XOR, 1'b1, 1'b0};
2'b11 : {EX_ALUFUNC, EX_WRREG_Z, EX_T_TSTSET} = {`ALU_OR , 1'b1, 1'b0};
default : ;
endcase
ID_INCPC = 1'b1;
ID_IF_ISSUE = 1'b1;
DISPATCH = 1'b1;
end
//----------------------
// CMP/STR Rm, Rn (2nmC)
//----------------------
4'b1100 : // 2xxC
begin
EX_RDREG_X = 1'b1;
EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
EX_RDREG_Y = 1'b1;
EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
EX_CMPCOM = INSTR_STATE[2:0];
EX_T_CMPSET = 1'b1;
ID_INCPC = 1'b1;
ID_IF_ISSUE = 1'b1;
DISPATCH = 1'b1;
end
//--------------------
// XTRCT Rm, Rn (2nmD)
//--------------------
4'b1101 : // 2xxD
begin
EX_RDREG_X = 1'b1;
EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
EX_RDREG_Y = 1'b1;
EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
EX_ALUFUNC = `ALU_XTRCT;
EX_WRREG_Z = 1'b1;
EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
ID_INCPC = 1'b1;
ID_IF_ISSUE = 1'b1;
DISPATCH = 1'b1;
end
//-----------------------------
// MULU/S.W Rm, Rn (2nmE/2nmF)
//-----------------------------
4'b111? : // 2nmE/2nmF
begin
MAC_STALL_SENSE = 1'b1;
EX_MAC_BUSY = (NEXT_ID_STALL)? 1'b0:1'b1;
EX_RDREG_X = 1'b1;
EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
EX_RDREG_Y = 1'b1;
EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
EX_MACSEL1 = 2'b00; // XBUS -> MACIN1
EX_MACSEL2 = 2'b00; // YBUS -> MACIN2
EX_MULCOM1 = 1'b1;
EX_MULCOM2 = {1'b1, INSTR_STATE[14:12], INSTR_STATE[3:0]};
ID_INCPC = 1'b1;
ID_IF_ISSUE = 1'b1;
DISPATCH = 1'b1;
end
//---------------
// Default = NOP
//---------------
default :
begin
ID_INCPC = 1'b1;
ID_IF_ISSUE = 1'b1;
DISPATCH = 1'b1;
end
endcase
//============================================
// Line 3xxx
//============================================
4'b0011 : // 3xxx
casex (INSTR_STATE[3:0])
//--------------------------------------------------------------
// CMP/xx Rm, Rn (EQ, HS, GE, HI, GT) (3nm0/3nm2/3nm3/3nm6/3nm7)
//--------------------------------------------------------------
4'b0000 : // 3xx0
begin
EX_RDREG_X = 1'b1;
EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
EX_RDREG_Y = 1'b1;
EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
EX_CMPCOM = INSTR_STATE[2:0];
EX_T_CMPSET = 1'b1;
ID_INCPC = 1'b1;
ID_IF_ISSUE = 1'b1;
DISPATCH = 1'b1;
end
4'b0?1? : // 3xx2, 3xx3, 3xx6, 3xx7
begin
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