decode.v

日立SH-2 CPU核的VERLOG源码

    //        CONST_IFDR <= IR[15:0];
    always @(posedge CLK)
        if (SLOT)
            CONST_IFDR <= INSTR_STATE;
//-----------------------------------
    reg EX_RDSR_X, RDSR_X;
    reg EX_RDSR_Y, RDSR_Y;
    reg EX_WRSR_Z, WRSR_Z;
    reg WB_WRSR_W, WRSR_W, WB1_WRSR_W, WB2_WRSR_W;
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            RDSR_X     <= 1'b0;
            RDSR_Y     <= 1'b0;
            WRSR_Z     <= 1'b0;
            WB1_WRSR_W <= 1'b0;
            WB2_WRSR_W <= 1'b0;
            WRSR_W     <= 1'b0;
        end
        else if (SLOT)
        begin
            RDSR_X     <= EX_RDSR_X;
            RDSR_Y     <= EX_RDSR_Y;
            WRSR_Z     <= ((NEXT_ID_STALL)? 1'b0 : EX_WRSR_Z);
            WB1_WRSR_W <= ((NEXT_ID_STALL)? 1'b0 : WB_WRSR_W);
            WB2_WRSR_W <= WB1_WRSR_W;
            WRSR_W     <= WB2_WRSR_W;
        end                                        
//-----------------------------------
    reg EX_RDGBR_X, RDGBR_X;
    reg EX_RDGBR_Y, RDGBR_Y;
    reg EX_WRGBR_Z, WRGBR_Z;
    reg WB_WRGBR_W, WRGBR_W, WB1_WRGBR_W, WB2_WRGBR_W;
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            RDGBR_X     <= 1'b0;
            RDGBR_Y     <= 1'b0;
            WRGBR_Z     <= 1'b0;
            WB1_WRGBR_W <= 1'b0;
            WB2_WRGBR_W <= 1'b0;
            WRGBR_W     <= 1'b0;
        end
        else if (SLOT)
        begin
            RDGBR_X     <= EX_RDGBR_X;
            RDGBR_Y     <= EX_RDGBR_Y;
            WRGBR_Z     <= ((NEXT_ID_STALL)? 1'b0 : EX_WRGBR_Z);
            WB1_WRGBR_W <= ((NEXT_ID_STALL)? 1'b0 : WB_WRGBR_W);
            WB2_WRGBR_W <= WB1_WRGBR_W;
            WRGBR_W     <= WB2_WRGBR_W;
        end
//-----------------------------------
    reg EX_RDVBR_X, RDVBR_X;
    reg EX_RDVBR_Y, RDVBR_Y;
    reg EX_WRVBR_Z, WRVBR_Z;
    reg WB_WRVBR_W, WRVBR_W, WB1_WRVBR_W, WB2_WRVBR_W;
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            RDVBR_X     <= 1'b0;
            RDVBR_Y     <= 1'b0;
            WRVBR_Z     <= 1'b0;
            WB1_WRVBR_W <= 1'b0;
            WB2_WRVBR_W <= 1'b0;
            WRVBR_W     <= 1'b0;
        end
        else if (SLOT)
        begin
            RDVBR_X     <= EX_RDVBR_X;
            RDVBR_Y     <= EX_RDVBR_Y;
            WRVBR_Z     <= ((NEXT_ID_STALL)? 1'b0 : EX_WRVBR_Z);
            WB1_WRVBR_W <= ((NEXT_ID_STALL)? 1'b0 : WB_WRVBR_W);
            WB2_WRVBR_W <= WB1_WRVBR_W;
            WRVBR_W     <= WB2_WRVBR_W;
        end
//-----------------------------------
    reg EX_RDPR_X, RDPR_X;
    reg EX_RDPR_Y, RDPR_Y;
    reg EX_WRPR_Z, WRPR_Z;
    reg WB_WRPR_W, WRPR_W, WB1_WRPR_W, WB2_WRPR_W;
    reg EX_WRPR_PC,WRPR_PC;
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            RDPR_X     <= 1'b0;
            RDPR_Y     <= 1'b0;
            WRPR_Z     <= 1'b0;
            WB1_WRPR_W <= 1'b0;
            WB2_WRPR_W <= 1'b0;
            WRPR_W     <= 1'b0;
            WRPR_PC    <= 1'b0;
        end
        else if (SLOT)
        begin
            RDPR_X     <= EX_RDPR_X;
            RDPR_Y     <= EX_RDPR_Y;
            WRPR_Z     <= ((NEXT_ID_STALL)? 1'b0 : EX_WRPR_Z);
            WB1_WRPR_W <= ((NEXT_ID_STALL)? 1'b0 : WB_WRPR_W);
            WB2_WRPR_W <= WB1_WRPR_W;
            WRPR_W     <= WB2_WRPR_W;
            WRPR_PC    <= ((NEXT_ID_STALL)? 1'b0 : EX_WRPR_PC);
        end
//-----------------------------------
    reg [2:0] EX_CMPCOM, CMPCOM;
    reg [4:0] EX_SFTFUNC, SFTFUNC;
    reg EX_RDSFT_Z, RDSFT_Z;
    reg EX_T_CMPSET, T_CMPSET;
    reg EX_T_CRYSET, T_CRYSET;
    reg EX_T_TSTSET, T_TSTSET;    
    reg EX_T_SFTSET, T_SFTSET;
    reg EX_QT_DV1SET, QT_DV1SET;
    reg EX_MQT_DV0SET, MQT_DV0SET;
    reg EX_T_CLR, T_CLR;
    reg EX_T_SET, T_SET;
    reg EX_MQ_CLR, MQ_CLR;

    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            RDSFT_Z    <= 1'b0;
            T_CMPSET   <= 1'b0;
            T_CRYSET   <= 1'b0;
            T_TSTSET   <= 1'b0;
            T_SFTSET   <= 1'b0;
            QT_DV1SET  <= 1'b0;
            MQT_DV0SET <= 1'b0;
            T_CLR      <= 1'b0;
            T_SET      <= 1'b0;
            MQ_CLR     <= 1'b0;
        end
        else if (SLOT)
        begin                                                  
            CMPCOM     <= ((NEXT_ID_STALL)? 3'b000 : EX_CMPCOM);   
            SFTFUNC    <= ((NEXT_ID_STALL)? 3'b000 : EX_SFTFUNC);
            RDSFT_Z    <= ((NEXT_ID_STALL)? 1'b0: EX_RDSFT_Z);
            T_CMPSET   <= ((NEXT_ID_STALL)? 1'b0: EX_T_CMPSET);
            T_CRYSET   <= ((NEXT_ID_STALL)? 1'b0: EX_T_CRYSET);
            T_TSTSET   <= ((NEXT_ID_STALL)? 1'b0: EX_T_TSTSET);
            T_SFTSET   <= ((NEXT_ID_STALL)? 1'b0: EX_T_SFTSET);
            QT_DV1SET  <= ((NEXT_ID_STALL)? 1'b0: EX_QT_DV1SET);
            MQT_DV0SET <= ((NEXT_ID_STALL)? 1'b0: EX_MQT_DV0SET);
            T_CLR      <= ((NEXT_ID_STALL)? 1'b0: EX_T_CLR);
            T_SET      <= ((NEXT_ID_STALL)? 1'b0: EX_T_SET);
            MQ_CLR     <= ((NEXT_ID_STALL)? 1'b0: EX_MQ_CLR);
        end                          
//-----------------------------------
    reg EX_RDTEMP_X,    RDTEMP_X;    
    reg EX_WRTEMP_Z,    WRTEMP_Z;
    reg EX_WRMAAD_TEMP, WRMAAD_TEMP;    
    reg EX_FWD_W2X,     FWD_W2X;     // force forward from W-bus to X-bus
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            RDTEMP_X    <= 1'b0;
            WRTEMP_Z    <= 1'b0;
            WRMAAD_TEMP <= 1'b0;
            FWD_W2X     <= 1'b0;
        end
        else if (SLOT)
        begin                                                   
            RDTEMP_X    <= ((NEXT_ID_STALL)? 1'b0: EX_RDTEMP_X);
            WRTEMP_Z    <= ((NEXT_ID_STALL)? 1'b0: EX_WRTEMP_Z);
            WRMAAD_TEMP <= ((NEXT_ID_STALL)? 1'b0: EX_WRMAAD_TEMP);
            FWD_W2X     <= ((NEXT_ID_STALL)? 1'b0: EX_FWD_W2X);
        end 

//-------------------
// Main State Machine
//-------------------
    // ----------------------Input State------------------ : ---Output--  ---@Next Slot---
    // SLOT  NEXT_ID_STALL  ID_STALL  DISPATCH  INSTR_SEQ  : INSTR_STATE  INSTR_SEQ  IR  
    // --------------------------------------------------- : -----------------------------
    // 0     *              *         *         *          : IR           Keep       Keep 
    // --------------------------------------------------- : -----------------------------
    // 1     0              0         0         >=0001     : IR           +1         Keep      
    // 1     0              0         0         ==0000     : IF_DR        +1         IF_DR
    // 1     0              0         1         >=0001     : IR           Clear0     Keep
    // 1     0              0         1         ==0000     : IF_DR        Clear0     IF_DR
    // 1     0              1         0         >=0001     : IR           +1         Keep      
    // 1     0              1         0         ==0000     : IR           +1         Keep
    // 1     0              1         1         >=0001     : IR           Clear0     Keep
    // 1     0              1         1         ==0000     : IR           Clear0     Keep
    // --------------------------------------------------- : -----------------------------
    // 1     1              0         0         >=0001     : IR           Keep       Keep
    // 1     1              0         0         ==0000     : IF_DR        Keep       IF_DR
    // 1     1              0         1         >=0001     : IR           Keep       Keep
    // 1     1              0         1         ==0000     : IF_DR        Keep       IF_DR
    // 1     1              1         0         >=0001     : IR           Keep       Keep
    // 1     1              1         0         ==0000     : IR           Keep       Keep
    // 1     1              1         1         >=0001     : IR           Keep       Keep
    // 1     1              1         1         ==0000     : IR           Keep       Keep
    //

    //-----------------------
    // Detect Exception Event
    //-----------------------
    always @(IF_DR or EVENT_REQ or EVENT_INFO or MASKINT or IBIT or DELAY_SLOT)
    begin
        //--------Hardware Event--------
        if (~DELAY_SLOT & (
               (~MASKINT & (EVENT_REQ == `NMI))
             | (~MASKINT & (EVENT_REQ == `IRQ) & (IBIT < EVENT_INFO[11:8]))
             | (EVENT_REQ == `CPUERR)
             | (EVENT_REQ == `DMAERR)
             | (EVENT_REQ == `MRES)
           ))
            begin
                IF_DR_EVT <= {5'b11110, EVENT_REQ, EVENT_INFO[7:0]};
            end
        //--------General & Slot Illegal Instruction--------
        else if (DELAY_SLOT)
            casex (IF_DR)
                16'b0000????00?00011 : IF_DR_EVT <= `SLOT_ILGL; // BSRF,BRAF
                16'b0000000000101011 : IF_DR_EVT <= `SLOT_ILGL; // RTE
                16'b0100????00?01011 : IF_DR_EVT <= `SLOT_ILGL; // JSR, JMP
                16'b10001??1???????? : IF_DR_EVT <= `SLOT_ILGL; // Bcc, Bcc/S
                16'b101????????????? : IF_DR_EVT <= `SLOT_ILGL; // RRA, BSR
                16'b11000011???????? : IF_DR_EVT <= `SLOT_ILGL; // TRAPA
                16'b11111111???????? : IF_DR_EVT <= `SLOT_ILGL; // General Illegal
                default              : IF_DR_EVT <= IF_DR;
            endcase
        else if (IF_DR[15:8] == 8'hFF)
                IF_DR_EVT <= `GNRL_ILGL; // General Illegal Instruction
        else
                IF_DR_EVT <= IF_DR;
    end
    //----------------------
    always @(posedge CLK)
    begin
        if (SLOT & ILEVEL_CAP) ILEVEL <= EVENT_INFO[11:8];
    end
    //----------------------
    always @(posedge CLK or posedge RST)
    begin
        if (RST)
            MASKINT <= 1'b0;
        else if (SLOT) 
            MASKINT <= MASKINT_NEXT;
    end
    //----------------------
    always @(posedge CLK or posedge RST)
    begin
        if (RST)
            DELAY_SLOT <= 1'b0;
        else if (SLOT)
            DELAY_SLOT <= (NEXT_ID_STALL)? DELAY_SLOT : DELAY_JUMP;
    end
    //----------------------
    always@ (EVENT_ACK_0 or SLOT) EVENT_ACK <= SLOT & EVENT_ACK_0;

    //---------------------
    // instruction register
    //---------------------
    always @(posedge CLK or posedge RST)
    begin
        if (RST)
            IR <= `POWERON_RESET;
        //else if ((SLOT & ~DISPATCH & INSTR_SEQ_ZERO) | (~SLOT & ~DISPATCH))
        else if (SLOT & ~ID_STALL & INSTR_SEQ_ZERO)
        begin
            IR <= IF_DR_EVT;
        end
    end

    //------------------
    // instruction state
    //------------------
    always @(ID_STALL or INSTR_SEQ_ZERO)
    begin
        case ({ID_STALL, INSTR_SEQ_ZERO})
            2'b00 : INSTR_STATE_SEL <= 1'b1;
            2'b01 : INSTR_STATE_SEL <= 1'b0;
            2'b10 : INSTR_STATE_SEL <= 1'b1;
            3'b11 : INSTR_STATE_SEL <= 1'b1;
            default : INSTR_STATE_SEL <= 1'bx;
        endcase
    end

    always @(INSTR_STATE_SEL or IR or IF_DR_EVT)
    begin
        if (INSTR_STATE_SEL) 
            INSTR_STATE <= IR;
        else
            INSTR_STATE <= IF_DR_EVT;
    end

    //--------------
    // Next ID STALL
    //--------------
    always @(REG_CONF or IF_STALL or MAC_STALL)
    begin
        if (REG_CONF | IF_STALL | MAC_STALL)
            NEXT_ID_STALL <= 1'b1;
        else
            NEXT_ID_STALL <= 1'b0;
    end

    //---------
    // ID STALL
    //---------
    always @(posedge CLK or posedge RST)
    begin
        if (RST)
            ID_STALL <= 1'b0;
        else if (SLOT)
            ID_STALL <= NEXT_ID_STALL;
    end
    
    //---------------------
    // instruction sequence
    //---------------------
    always @(posedge CLK or posedge RST) begin
        if (RST)
            INSTR_SEQ <= 4'b0001;
        else if (SLOT & ~NEXT_ID_STALL & DISPATCH)
            INSTR_SEQ <= 4'b0000;
        else if (SLOT & ~NEXT_ID_STALL & ~DISPATCH)
            INSTR_SEQ <= INSTR_SEQ + 1;
    end

    always @(INSTR_SEQ)
    begin
        if (INSTR_SEQ == 4'b0000)
            INSTR_SEQ_ZERO <= 1'b1;
        else
            INSTR_SEQ_ZERO <= 1'b0;
    end

    //------------------------