decode.v

日立SH-2 CPU核的VERLOG源码

          or WB1_MAC_BUSY or WB2_MAC_BUSY or WB3_MAC_BUSY or EX1_MAC_BUSY)
    begin
        MAC_STALL <= MAC_STALL_SENSE 
                   & (WB1_MAC_BUSY | WB2_MAC_BUSY | WB3_MAC_BUSY | EX1_MAC_BUSY | MAC_BUSY);
    end

//-----------------------------------
// Control Signal & Pipeline Shifting
//-----------------------------------
// Examples of Naming Convention
//    ID_ddd  : control signal for ID stage (output by Decoder)
//    EX_eee  : control signal for EX stage (output by Decoder)
//    eee     : shifted EX_eee by one slot (control output to datapath) 
//    WB_www  : control signal for WB stage (output by Decoder)
//    WB1_www : shifted WB_www by one slot (active at EX stage)
//    WB2_www : shifted WB1_www by one slot (active at MA stage)
//    www     : shifted WB2_www by one slot (control output to datapath) 
//                                   
//-----------------------------------
    reg [1:0] WB_MACSEL1, WB1_MACSEL1, WB2_MACSEL1, EX_MACSEL1, MACSEL1;
    reg WB_MULCOM1, WB1_MULCOM1, WB2_MULCOM1, EX_MULCOM1, MULCOM1;
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            WB1_MULCOM1 <= 1'b0;
            WB2_MULCOM1 <= 1'b0;
            MULCOM1     <= 1'b0;
            WB1_MACSEL1 <= 2'b00;
            WB2_MACSEL1 <= 2'b00;
            MACSEL1     <= 2'b00;
        end
        else if (SLOT)
        begin
            WB1_MULCOM1 <= ((NEXT_ID_STALL)? 1'b0 : WB_MULCOM1);
            WB2_MULCOM1 <= WB1_MULCOM1;
            MULCOM1     <= WB2_MULCOM1 | ((NEXT_ID_STALL)? 1'b0 : EX_MULCOM1);
            WB1_MACSEL1 <= ((NEXT_ID_STALL)? 1'b0 : WB_MACSEL1);
            WB2_MACSEL1 <= WB1_MACSEL1;
            MACSEL1     <= WB2_MACSEL1 | ((NEXT_ID_STALL)? 1'b0 : EX_MACSEL1);
        end
        
    reg [1:0] WB_MACSEL2, WB1_MACSEL2, WB2_MACSEL2, EX_MACSEL2, MACSEL2;
    reg [7:0] WB_MULCOM2, WB1_MULCOM2, WB2_MULCOM2, EX_MULCOM2, MULCOM2;
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            WB1_MULCOM2 <= 8'h00;
            WB2_MULCOM2 <= 8'h00;
            MULCOM2     <= 8'h00;
            WB1_MACSEL2 <= 2'b00;
            WB2_MACSEL2 <= 2'b00;
            MACSEL2     <= 2'b00;
        end
        else if (SLOT)
        begin
            WB1_MULCOM2 <= ((NEXT_ID_STALL)? 1'b0 : WB_MULCOM2);
            WB2_MULCOM2 <= WB1_MULCOM2;
            MULCOM2     <= WB2_MULCOM2 | ((NEXT_ID_STALL)? 1'b0 : EX_MULCOM2);
            WB1_MACSEL2 <= ((NEXT_ID_STALL)? 1'b0 : WB_MACSEL2);
            WB2_MACSEL2 <= WB1_MACSEL2;
            MACSEL2     <= WB2_MACSEL2 | ((NEXT_ID_STALL)? 1'b0 : EX_MACSEL2);
        end                                                             
//-----------------------------------
    reg EX_RDMACH_X, RDMACH_X;
    reg EX_RDMACL_X, RDMACL_X;
    reg EX_RDMACH_Y, RDMACH_Y;
    reg EX_RDMACL_Y, RDMACL_Y;
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
             RDMACH_X <= 1'b0;
             RDMACL_X <= 1'b0;
             RDMACH_Y <= 1'b0;
             RDMACL_Y <= 1'b0;
        end
        else if (SLOT)
        begin
             RDMACH_X <= EX_RDMACH_X;
             RDMACL_X <= EX_RDMACL_X;
             RDMACH_Y <= EX_RDMACH_Y;
             RDMACL_Y <= EX_RDMACL_Y;
        end

    reg WB_WRMACH, EX_WRMACH, WRMACH, WB1_WRMACH, WB2_WRMACH;
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            WB1_WRMACH <= 1'b0;
            WB2_WRMACH <= 1'b0;
            WRMACH     <= 1'b0;
        end
        else if (SLOT)
        begin
            WB1_WRMACH <= ((NEXT_ID_STALL)? 1'b0 : WB_WRMACH);
            WB2_WRMACH <= WB1_WRMACH;
            WRMACH     <= WB2_WRMACH | ((NEXT_ID_STALL)? 1'b0 : EX_WRMACH);
        end

    reg WB_WRMACL, EX_WRMACL, WRMACL, WB1_WRMACL, WB2_WRMACL;
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            WB1_WRMACL <= 1'b0;
            WB2_WRMACL <= 1'b0;
            WRMACL     <= 1'b0;
        end
        else if (SLOT)
        begin
            WB1_WRMACL <= ((NEXT_ID_STALL)? 1'b0 : WB_WRMACL);
            WB2_WRMACL <= WB1_WRMACL;
            WRMACL     <= WB2_WRMACL | ((NEXT_ID_STALL)? 1'b0 : EX_WRMACL);
        end
//-----------------------------------
    reg EX_RDREG_X, RDREG_X;
    reg EX_RDREG_Y, RDREG_Y;
    reg [3:0] EX_REGNUM_X, REGNUM_X;
    reg [3:0] EX_REGNUM_Y, REGNUM_Y;
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            RDREG_X <= 1'b0;
            RDREG_Y <= 1'b0;
        end
        else if (SLOT)
        begin
            RDREG_X  <= EX_RDREG_X;
            RDREG_Y  <= EX_RDREG_Y;
            REGNUM_X <= EX_REGNUM_X;
            REGNUM_Y <= EX_REGNUM_Y;
        end

    reg EX_WRREG_Z, WRREG_Z;
    reg [3:0] EX_REGNUM_Z, REGNUM_Z;
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            WRREG_Z  <= 1'b0;
        end
        else if (SLOT)
        begin
            WRREG_Z  <= ((NEXT_ID_STALL)? 1'b0 : EX_WRREG_Z);
            REGNUM_Z <= EX_REGNUM_Z;
        end

    reg WB_WRREG_W, WRREG_W, WB1_WRREG_W, WB2_WRREG_W;
    reg [3:0] WB_REGNUM_W, REGNUM_W, WB1_REGNUM_W, WB2_REGNUM_W;
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            WB1_WRREG_W  <= 1'b0;
            WB2_WRREG_W  <= 1'b0;
            WRREG_W      <= 1'b0;
        end
        else if (SLOT) begin
            WB1_WRREG_W  <= ((NEXT_ID_STALL)? 1'b0 : WB_WRREG_W);
            WB2_WRREG_W  <= WB1_WRREG_W;
            WRREG_W      <= WB2_WRREG_W;
            WB1_REGNUM_W <= WB_REGNUM_W;
            WB2_REGNUM_W <= WB1_REGNUM_W;
            REGNUM_W     <= WB2_REGNUM_W;
        end
//-----------------------------------
    reg [4:0] EX_ALUFUNC, ALUFUNC;
    always @(posedge CLK or posedge RST)
        if (RST)
            ALUFUNC <= `ALU_NOP;
        else if (SLOT) begin
            ALUFUNC <= EX_ALUFUNC;
        end
//-----------------------------------
    reg EX_WRMAAD_Z, WRMAAD_Z;
    reg EX_WRMADW_X, WRMADW_X;
    reg EX_WRMADW_Y, WRMADW_Y;
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            WRMAAD_Z <= 1'b0;
            WRMADW_X <= 1'b0;
            WRMADW_Y <= 1'b0;
        end
        else if (SLOT)
        begin
            WRMAAD_Z <= ((NEXT_ID_STALL)? 1'b0 : EX_WRMAAD_Z);
            WRMADW_X <= ((NEXT_ID_STALL)? 1'b0 : EX_WRMADW_X); 
            WRMADW_Y <= ((NEXT_ID_STALL)? 1'b0 : EX_WRMADW_Y);
        end

    reg WB_RDMADR_W, RDMADR_W, WB1_RDMADR_W, WB2_RDMADR_W;
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            WB1_RDMADR_W <= 1'b0;
            WB2_RDMADR_W <= 1'b0;
            RDMADR_W     <= 1'b0;
        end
        else if (SLOT)
        begin
            WB1_RDMADR_W <= WB_RDMADR_W;
            WB2_RDMADR_W <= WB1_RDMADR_W;
            RDMADR_W     <= WB2_RDMADR_W;
        end
//-----------------------------------
    reg EX_RDPC_X, RDPC_X;
    reg EX_RDPC_Y, RDPC_Y;
    reg EX_WRPC_Z, WRPC_Z;
    reg ID_INCPC, INCPC;
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            RDPC_X <= 1'b0;
            RDPC_Y <= 1'b0;
            WRPC_Z <= 1'b0;
        end
        else if (SLOT)
        begin
            RDPC_X <= EX_RDPC_X;
            RDPC_Y <= EX_RDPC_Y;
            WRPC_Z <= ((NEXT_ID_STALL)? 1'b0 : EX_WRPC_Z);
        end

    always @(ID_INCPC or NEXT_ID_STALL)
    begin
        INCPC <= ((NEXT_ID_STALL)? 1'b0 : ID_INCPC);
    end

    reg EX_IFADSEL, ID_IFADSEL, IFADSEL, EX1_IFADSEL;
    always @(posedge CLK or posedge RST)
        if (RST)
            EX1_IFADSEL <= 1'b0;
        else if (SLOT) begin
            EX1_IFADSEL <= EX_IFADSEL;
        end

    always @(EX1_IFADSEL or ID_IFADSEL)
        IFADSEL <= EX1_IFADSEL | ID_IFADSEL;

    reg  EX_IF_ISSUE, ID_IF_ISSUE, IF_ISSUE, EX1_IF_ISSUE;  // fetch request
    reg  EX_IF_JP, ID_IF_JP, IF_JP, EX1_IF_JP;              // fetch caused by jump
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            EX1_IF_ISSUE <= 1'b0;
            EX1_IF_JP    <= 1'b0;
        end
        else if (SLOT) begin
            EX1_IF_ISSUE <= ((NEXT_ID_STALL)? 1'b0 : EX_IF_ISSUE);
            EX1_IF_JP    <= ((NEXT_ID_STALL)? 1'b0 : EX_IF_JP);
        end

    // [CAUTION]
    // IF_ISSUE and IF_JP should be masked by REG_CONF.
    // If they are masked by NEXT_ID_STALL which is made from IF_STALL, 
    // a oscillation loop from DECODE--(issue command)-->MEM--(IF_STALL)-->DECODE appears.
    // The IF issue operation is stalled only by register conflict stall, so
    // this function is correct.
    // And also, IF_ISSUE should be masked by MAC_STALL, because, if the ID stage of instruction
    // stalled by MAC_STALL issues IF at every stalled cycle, the fetched instruction 
    // may be diappeared.
    always @(EX1_IF_ISSUE or ID_IF_ISSUE or EX1_IF_JP or ID_IF_JP or REG_CONF or MAC_STALL)
    begin
        IF_ISSUE <= EX1_IF_ISSUE | (ID_IF_ISSUE & ~REG_CONF & ~MAC_STALL);
        IF_JP <= EX1_IF_JP | (ID_IF_JP & ~REG_CONF);
    end
//-----------------------------------
    reg  EX_MA_ISSUE, MA_ISSUE;   // memory access request
    reg  EX_KEEP_CYC, KEEP_CYC;   // request read-modify-write (To be issued on READ-CYC to keep CYC_O on)
    reg  EX_MA_WR, MA_WR;         // memory access kind : Write(1)/Read(0)
    reg  [1:0] EX_MA_SZ, MA_SZ;   // memory access size : 00 byte, 01 word, 10 long, 11 inhibitted
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            MA_ISSUE <= 1'b0;
            KEEP_CYC <= 1'b0;
            MA_WR    <= 1'b0;
            MA_SZ    <= 2'b00;
        end
        else if (SLOT)
        begin
            MA_ISSUE <= ((NEXT_ID_STALL)? 1'b0 : EX_MA_ISSUE);
            KEEP_CYC <= EX_KEEP_CYC;
            MA_WR <= EX_MA_WR;
            MA_SZ <= EX_MA_SZ;
        end
//-----------------------------------
    reg EX_CONST_ZERO4,  CONST_ZERO4;  
    reg EX_CONST_ZERO42, CONST_ZERO42;
    reg EX_CONST_ZERO44, CONST_ZERO44;
    reg EX_CONST_ZERO8,  CONST_ZERO8;  
    reg EX_CONST_ZERO82, CONST_ZERO82;
    reg EX_CONST_ZERO84, CONST_ZERO84;
    reg EX_CONST_SIGN8,  CONST_SIGN8;  
    reg EX_CONST_SIGN82, CONST_SIGN82;
    reg EX_CONST_SIGN122,CONST_SIGN122;
    reg EX_RDCONST_X, RDCONST_X;
    reg EX_RDCONST_Y, RDCONST_Y;
    always @(posedge CLK or posedge RST)
        if (RST)
        begin
            CONST_ZERO4  <= 1'b0;
            CONST_ZERO42 <= 1'b0;
            CONST_ZERO44 <= 1'b0;  
            CONST_ZERO8  <= 1'b0;
            CONST_ZERO82 <= 1'b0;
            CONST_ZERO84 <= 1'b0;
            CONST_SIGN8  <= 1'b0;
            CONST_SIGN82 <= 1'b0;
            CONST_SIGN122<= 1'b0; 
            RDCONST_X    <= 1'b0;
            RDCONST_Y    <= 1'b0;
        end
        else if (SLOT)
        begin
            CONST_ZERO4  <= EX_CONST_ZERO4;
            CONST_ZERO44 <= EX_CONST_ZERO44;
            CONST_ZERO42 <= EX_CONST_ZERO42;
            CONST_ZERO8  <= EX_CONST_ZERO8; 
            CONST_ZERO82 <= EX_CONST_ZERO82;
            CONST_ZERO84 <= EX_CONST_ZERO84;
            CONST_SIGN8  <= EX_CONST_SIGN8; 
            CONST_SIGN82 <= EX_CONST_SIGN82;
            CONST_SIGN122<= EX_CONST_SIGN122;
            RDCONST_X    <= EX_RDCONST_X;
            RDCONST_Y    <= EX_RDCONST_Y;
        end

    reg [15:0] CONST_IFDR;
    //always @(posedge CLK)
    //    if (SLOT & INSTR_SEQ_ZERO & ~NEXT_ID_STALL)
    //        CONST_IFDR <= IF_DR[15:0];
    //    else if (SLOT & ~INSTR_SEQ_ZERO & ~NEXT_ID_STALL)