decode.v

日立SH-2 CPU核的VERLOG源码

//======================================================
// Aquarius Project
//    SuperH-2 ISA Compatible RISC CPU
//------------------------------------------------------
// Module      : Decode Unit
//------------------------------------------------------
// File        : decode.v
// Library     : none
// Description : Decode Unit in CPU.
// Simulator   : Icarus Verilog (Cygwin)
// Synthesizer : Xilinx XST (Windows XP)
// Author      : Thorn Aitch
//------------------------------------------------------
// Revision Number : 1
// Date of Change  : 8th April 2002
// Creator         : Thorn Aitch
// Description     : Initial Design				  
//------------------------------------------------------
// Revision Number : 2
// Date of Change  : 11th August 2002
// Modifier        : Thorn Aitch
// Description     : Have Checked Memory Controller I/F					  
//------------------------------------------------------
// Revision Number : 3
// Date of Change  : 30th April 2003
// Modifier        : Thorn Aitch
// Description     : Release Version 1.0  
//------------------------------------------------------
// Revision Number : 4
// Date of Change  : 10th December 2003
// Modifier        : Thorn Aitch
// Description     : Release Version 1.1
//                   Inhibit substitution of "x"
//                   except for defalut statement whose
//                   case describes all logic spaces. 
//======================================================
// Copyright (C) 2002-2003, Thorn Aitch
//
// Designs can be altered while keeping list of
// modifications "the same as in GNU" No money can
// be earned by selling the designs themselves, but
// anyone can get money by selling the implementation
// of the design, such as ICs based on some cores, 
// boards based on some schematics or Layouts, and
// even GUI interfaces to text mode drivers.
// "The same as GPL SW" Any update to the design
// should be documented and returned to the design. 
// Any derivative work based on the IP should be free
// under OpenIP License. Derivative work means any
// update, change or improvement on the design. 
// Any work based on the design can be either made
// free under OpenIP license or protected by any other
// license. Work based on the design means any work uses
// the OpenIP Licensed core as a building black without
// changing anything on it with any other blocks to
// produce larger design.  There is NO WARRANTY on the
// functionality or performance of the design on the
// real hardware implementation.
// On the other hand, the SuperH-2 ISA (Instruction Set
// Architecture) executed by Aquarius is rigidly
// the property of Renesas Corp. Then you have all 
// responsibility to judge if there are not any 
// infringements to Renesas's rights regarding your 
// Aquarius adoption into your design. 
// By adopting Aquarius, the user assumes all 
// responsibility for its use.
// This project may cause any damages around you, for 
// example, loss of properties, data, money, profits,
// life, or business etc. By adopting this source, 
// the user assumes all responsibility for its use.
//======================================================

`include "timescale.v"
`include "defines.v"

//*************************************************
// Module Definition
//*************************************************
module decode(
    // system signal
    CLK, RST, SLOT,
    // instruction fetch control
    IF_ISSUE, IF_JP,
    IF_DR, IF_BUS, IF_STALL,
    // data access control
    MA_ISSUE, KEEP_CYC, MA_WR, MA_SZ,
    //
    // multplier
    //
    // mult command
    MULCOM1, MULCOM2, WRMACH, WRMACL,
    // mult busy signal
    MAC_BUSY,
    //
    // data path
    //
    // general register
    RDREG_X,  RDREG_Y,  WRREG_Z,  WRREG_W,
    REGNUM_X, REGNUM_Y, REGNUM_Z, REGNUM_W,
    // ALU function
    ALUFUNC,
    // memory access
    WRMAAD_Z, WRMADW_X, WRMADW_Y, RDMADR_W,
    // mult
    MACSEL1, MACSEL2,
    RDMACH_X, RDMACL_X,
    RDMACH_Y, RDMACL_Y,
    // status register
    RDSR_X, RDSR_Y,
    WRSR_Z, WRSR_W,      
    // S bit for MAC
    MAC_S_LATCH,
    // global base register
    RDGBR_X, RDGBR_Y,
    WRGBR_Z, WRGBR_W,
    // vector base register
    RDVBR_X, RDVBR_Y,
    WRVBR_Z, WRVBR_W,
    // procedure register
    RDPR_X, RDPR_Y,
    WRPR_Z, WRPR_W, WRPR_PC,
    // program counter
    RDPC_X, RDPC_Y, WRPC_Z,
    INCPC, IFADSEL,
    // make constant
    CONST_IFDR, 
    CONST_ZERO4, CONST_ZERO42, CONST_ZERO44,                         
    CONST_ZERO8, CONST_ZERO82, CONST_ZERO84,
    CONST_SIGN8, CONST_SIGN82, CONST_SIGN122,
    RDCONST_X, RDCONST_Y,
    // register forward
    REG_FWD_X, REG_FWD_Y,
    // commands for comparator and shifter
    CMPCOM, SFTFUNC,
    // read controls to Z-BUS
    RDSFT_Z, 
    // T value for Bcc judgement
    T_BCC,
    // SR control
    T_CMPSET, T_CRYSET, T_TSTSET, T_SFTSET,
    QT_DV1SET, MQT_DV0SET, T_CLR, T_SET, MQ_CLR,
    // Temporary Register
    RDTEMP_X,
    WRTEMP_Z, WRMAAD_TEMP,
    // Hardware Exception Event
    EVENT_REQ, EVENT_ACK, EVENT_INFO,
    // I bit in Status Register
    RST_SR, IBIT, ILEVEL, WR_IBIT,
    // SLEEP
    SLP
    );

//-------------------
// Module I/O Signals
//-------------------
    input  CLK;            // clock
    input  RST;            // reset
    input  SLOT;           // pipeline slot
    output IF_ISSUE;       // fetch request
    output IF_JP;          // fetch caused by jump
    input  [15:0] IF_DR;   // fetched instruction
    input  IF_BUS;         // fetch access done to extenal bus
    input  IF_STALL;       // fetch and memory access contention
    output MA_ISSUE;       // memory access request
    output KEEP_CYC;       // request read-modify-write (To be issued on READ-CYC to keep CYC_O on)
    output MA_WR;          // memory access kind : Write(1)/Read(0)
    output [1:0] MA_SZ;    // memory access size : 00 byte, 01 word, 10 long, 11 inhibitted

    output MULCOM1;        // Mult M1 Latch Command
    output [7:0] MULCOM2;  // Mult M2 Latch Command
    output WRMACH, WRMACL; // Write MACH/MACL
    input  MAC_BUSY;       // multiplier busy signal (negate at final operation state)

    output RDREG_X;        // read REG to X
    output RDREG_Y;        // read REG to Y
    output WRREG_Z;        // write REG from Z
    output WRREG_W;        // write REG from W

    output [3:0] REGNUM_X; // specify REG number reading to X
    output [3:0] REGNUM_Y; // specify REG number reading to Y
    output [3:0] REGNUM_Z; // specify REG number writing from Z
    output [3:0] REGNUM_W; // specify REG number writing from W

    output [4:0] ALUFUNC;  // ALU function

    output WRMAAD_Z;       // write MAAD from Z
    output WRMADW_X;       // write MADW from X
    output WRMADW_Y;       // write MADW from Y
    output RDMADR_W;       // read MADR to W

    output [1:0] MACSEL1;  // MAC Selecter 1
    output [1:0] MACSEL2;  // MAC Selecter 2
    output RDMACH_X;       // read MACH to X
    output RDMACL_X;       // read MACL to X
    output RDMACH_Y;       // read MACH to Y
    output RDMACL_Y;       // read MACL to Y
    
    output RDSR_X;         // read SR to X-bus
    output RDSR_Y;         // read SR to Y-bus
    output WRSR_Z;         // write SR from Z-bus
    output WRSR_W;         // write SR from W-bus

    output MAC_S_LATCH;    // latch S bit before MAC operation
                                                    
    output RDGBR_X;        // read GBR to X-bus
    output RDGBR_Y;        // read GBR to Y-bus
    output WRGBR_Z;        // write GBR from Z-bus
    output WRGBR_W;        // write GBR from W-bus

    output RDVBR_X;        // read VBR to X-bus
    output RDVBR_Y;        // read VBR to Y-bus
    output WRVBR_Z;        // write VBR from Z-bus
    output WRVBR_W;        // write VBR from W-bus

    output RDPR_X;         // read PR to X-bus
    output RDPR_Y;         // read PR to Y-bus
    output WRPR_Z;         // write PR from Z-bus
    output WRPR_W;         // write PR from W-bus
    output WRPR_PC;        // write PR from PC

    output RDPC_X;         // read PC to X
    output RDPC_Y;         // read PC to Y
    output WRPC_Z;         // write PC from Z
    output INCPC;          // increment PC
    output IFADSEL;        // IF_AD selecter

    output [15:0] CONST_IFDR; // Constant Value from Instruction Field
    output CONST_ZERO4;       // Const = unsigned lower 4bit
    output CONST_ZERO42;      // Const = unsigned lower 4bit * 2
    output CONST_ZERO44;      // Const = unsigned lower 4bit * 4
    output CONST_ZERO8;       // Const = unsigned lower 8bit
    output CONST_ZERO82;      // Const = unsigned lower 8bit * 2
    output CONST_ZERO84;      // Const = unsigned lower 8bit * 4
    output CONST_SIGN8;       // Const = signed lower 8bit
    output CONST_SIGN82;      // Const = signed lower 8bit * 2
    output CONST_SIGN122;     // Const = signed lower 12bit * 2
    output RDCONST_X;         // read CONST to X
    output RDCONST_Y;         // read CONST to Y
    output REG_FWD_X;         // forward REG from W to X
    output REG_FWD_Y;         // forward REG from W to Y

    output [2:0] CMPCOM;   // define comparator operation (command)
    output [4:0] SFTFUNC;  // Shifter Function

    output RDSFT_Z;        // read SFTOUT to Z-BUS

    input  T_BCC;          // T value for Bcc judgement
    output T_CMPSET;       // reflect comparator result to T
    output T_CRYSET;       // reflect carry/borrow out to T
    output T_TSTSET;       // reflect tst result to T
    output T_SFTSET;       // reflect shifted output to T
    output QT_DV1SET;      // reflect DIV1 result to Q and T
    output MQT_DV0SET;     // reflect DIV0S result to M, Q and T
    output T_CLR;          // clear T
    output T_SET;          // set T
    output MQ_CLR;         // clear M and Q

    output RDTEMP_X;       // read TEMP to X-bus
    output WRTEMP_Z;       // write to TEMP from Z-bus
    output WRMAAD_TEMP;    // output MAAD from TEMP

    input  [2:0] EVENT_REQ;   // event request
    output EVENT_ACK;         // event acknowledge
    input  [11:0] EVENT_INFO; // event information (ILEVEL[3:0],VECTOR[7:0])

    output RST_SR;         // reset SR
    input  [3:0] IBIT;     // I bit in SR
    output [3:0] ILEVEL;   // IRQ Level
    output WR_IBIT;        // Write ILEVEL to I bit in SR

    output SLP;            // Sleep output

//-----------------
// Internal Signals
//-----------------
    reg  [15:0] IF_DR_EVT; // IF_DR reflected by Hardware Event
    reg  EVENT_ACK;        // Hardware Event Acknowledge 
    reg  EVENT_ACK_0;      // Hardware Event Acknowledge from huge truth table
    reg  [15:0] IR;     // instruction register
                        // It is used by only multicycle instruction.
                        // IF_DR is latched to IR when INSTR_SEQ=0.
                        // This means IR is valid after ID stage (=from EX stage).
    reg  [15:0] INSTR_STATE; // Instruction State (what instruction is on going.)
    reg  [ 3:0] INSTR_SEQ;   // Instruction Sequence
    reg  DISPATCH;      // clear INSTR_SEQ (restart sequence for new instruction)
    reg  REG_CONF;      // register conflict (memory load contention)
    reg  ID_STALL;      // indicate a slot of stalled ID stage 
    reg  NEXT_ID_STALL; // indicate next ID should be stalled 
    reg  INSTR_SEQ_ZERO;// if (INSTR_SEQ == 4'b0000) INSTR_SEQ_ZERO is 1 else 0
    reg  INSTR_STATE_SEL; // 0:INSTR_STATE=IFDR, 1:INSTRSTATE=IR
    reg  DELAY_JUMP;    // it shows ID stage of delayed jump instruction
    reg  DELAY_SLOT;    // it shows ID stage of delayed slot instruction

    reg  RST_SR;        // reset SR
    reg  [3:0] ILEVEL;  // IRQ Level
    reg  ILEVEL_CAP;    // Capture IRQ Level
    reg  WR_IBIT;       // Write ILEVEL to I bit in SR
    reg  MASKINT_NEXT;  // Mask Interrupt at next slot
    reg  MASKINT;       // Mask Interrupt at this slot

    reg  SLP;           // Sleep output

//---------------------------------
// Multiplier related Stall Control
//---------------------------------
    reg  WB_MAC_BUSY, WB1_MAC_BUSY, WB2_MAC_BUSY, WB3_MAC_BUSY;
    reg  EX_MAC_BUSY, EX1_MAC_BUSY;
    reg  MAC_STALL;       // Shows "should-be-stalled" ID of multiplier related instruction.
    reg  MAC_STALL_SENSE; // ID stage that is stalled by multiplier operation should set this.
    reg  MAC_S_LATCH;     // command to latch S bit before MAC operation

    always @(posedge CLK or posedge RST)
    begin
        if (RST)
        begin
            WB1_MAC_BUSY <= 1'b0;
            WB2_MAC_BUSY <= 1'b0;
            WB3_MAC_BUSY <= 1'b0;
            EX1_MAC_BUSY <= 1'b0;
        end
        else if (SLOT)
        begin
            WB1_MAC_BUSY <= WB_MAC_BUSY;
            WB2_MAC_BUSY <= WB1_MAC_BUSY;
            WB3_MAC_BUSY <= WB2_MAC_BUSY;
            EX1_MAC_BUSY <= EX_MAC_BUSY;    
        end
    end

    always @(MAC_STALL_SENSE or MAC_BUSY