datapath.v

日立SH-2 CPU核的VERLOG源码

                         CMPRESULT <= 1'b0;
            `CMPHI : //110 higher than    (unsigned)
                     if ( (EQMSB & HI)
                        | ((XBUS[31] == 1'b1) & (YBUS[31] == 1'b0)) )
                         CMPRESULT <= 1'b1;
                     else
                         CMPRESULT <= 1'b0;  
            `CMPGT : //111 grater than    (signed) 
                     if ( (EQMSB & HI)
                        | ((XBUS[31] == 1'b0) & (YBUS[31] == 1'b1)) )
                         CMPRESULT <= 1'b1;
                     else
                         CMPRESULT <= 1'b0;
            `CMPPL : //101 plus (not 0)   (signed)
                     CMPRESULT <= ~XBUS[31] & ~(EQMSB & EQ);
            `CMPPZ : //001 plus or zero   (signed)
                     CMPRESULT <= ~XBUS[31] | (EQMSB & EQ);
            `CMPSTR: //100 equal at least 1 byte
                         CMPRESULT <= (EQMSB & EQHH) | EQHL | EQLH | EQLL;
            default : CMPRESULT <= 1'b0;
        endcase
    end

//-----------------
// Shifter Function
//-----------------
    always @(SFTFUNC or XBUS or SR)
    begin
        case (SFTFUNC)
            `SHLL   : SFTOUT <= {XBUS[30:0], 1'b0};
            `SHAL   : SFTOUT <= {XBUS[30:0], 1'b0};
            `SHLR   : SFTOUT <= {1'b0, XBUS[31:1]};
            `SHAR   : SFTOUT <= {XBUS[31], XBUS[31:1]};
            `ROTL   : SFTOUT <= {XBUS[30:0], XBUS[31]};
            `ROTCL  : SFTOUT <= {XBUS[30:0], SR[`T]};
            `ROTR   : SFTOUT <= {XBUS[0], XBUS[31:1]};
            `ROTCR  : SFTOUT <= {SR[`T], XBUS[31:1]};
            `SHLL2  : SFTOUT <= {XBUS[29:0], 2'b00};
            `SHLL8  : SFTOUT <= {XBUS[23:0], 8'h00};
            `SHLL16 : SFTOUT <= {XBUS[15:0], 16'h0000};
            `SHLR2  : SFTOUT <= {2'b00, XBUS[31:2]};
            `SHLR8  : SFTOUT <= {8'h00, XBUS[31:8]};
            `SHLR16 : SFTOUT <= {16'h0000, XBUS[31:16]};
            default: SFTOUT <= 32'hxxxxxxxx;
        endcase
        case (SFTFUNC)
            `SHLL   : SFTO <= XBUS[31];
            `SHAL   : SFTO <= XBUS[31];
            `SHLR   : SFTO <= XBUS[0];
            `SHAR   : SFTO <= XBUS[0];
            `ROTL   : SFTO <= XBUS[31];
            `ROTCL  : SFTO <= XBUS[31];
            `ROTR   : SFTO <= XBUS[0];
            `ROTCR  : SFTO <= XBUS[0];
            default: SFTO <= 1'bx;
        endcase
    end

//---------------
// Output to Mult
//---------------
    always @(MACSEL1 or XBUS or ZBUS or WBUS)
    begin
        casex (MACSEL1)
            2'b00   : MACIN1 <= XBUS;
            2'b01   : MACIN1 <= ZBUS;
            2'b1?   : MACIN1 <= WBUS;
            default : MACIN1 <= WBUS;
        endcase
    end

    always @(MACSEL2 or YBUS or ZBUS or WBUS)
    begin
        casex (MACSEL2)
            2'b00   : MACIN2 <= YBUS;
            2'b01   : MACIN2 <= ZBUS;
            2'b1?   : MACIN2 <= WBUS;
            default : MACIN2 <= WBUS;
        endcase
    end

//------------------------
// Memory Access Interface
//------------------------
    always @(WRMAAD_Z or ZBUS or WRMAAD_TEMP or TEMP or XBUS)
    begin
        if (WRMAAD_Z)
            MA_AD <= ZBUS;
        else if (WRMAAD_TEMP)
            MA_AD <= TEMP;
        else
            MA_AD <= XBUS; // default MA_AD is XBUS
    end

    always @(WRMADW_X or WRMADW_Y or XBUS or YBUS or ZBUS)
    begin
        if (WRMADW_X)
            MA_DW <= XBUS;
        else if (WRMADW_Y)
            MA_DW <= YBUS;
        else
            MA_DW <= ZBUS;
    end

//---------------------
// Program Counter : PC
//---------------------
    always @(posedge CLK)
    begin
        if (SLOT)
        begin
            if (WRPC_Z)
                PC <= ZBUS;
            else if (INCPC)
                PC <= PCADD2;
        end
    end

    always @(PC)
    begin
        PCADD2 <= PC + 2;
    end

    always @(IFADSEL or PCADD2 or ZBUS)
    begin
        if (IFADSEL == 1'b0)
            IF_AD <= PCADD2;
        else
            IF_AD <= ZBUS;
    end

//---------
// Constant
//---------
    always @(CONST_IFDR
          or CONST_ZERO4 or CONST_ZERO42 or CONST_ZERO44
          or CONST_ZERO8 or CONST_ZERO82 or CONST_ZERO84
          or CONST_SIGN8 or CONST_SIGN82
          or CONST_SIGN122)
    begin
        if (CONST_ZERO4)
            begin
                CONST[31:4] <= 28'h0000000;
                CONST[ 3:0] <= CONST_IFDR[3:0];
            end                          
        else if (CONST_ZERO42)
            begin
                CONST[31:5] <= 27'h0000000;
                CONST[ 4:1] <= CONST_IFDR[3:0];
                CONST[   0] <= 1'b0;    
            end                          
        else if (CONST_ZERO44)
            begin
                CONST[31:6] <= 26'h0000000;
                CONST[ 5:2] <= CONST_IFDR[3:0];
                CONST[ 1:0] <= 2'b00;    
            end
        else if (CONST_ZERO8)
            begin
                CONST[31:8] <= 24'h000000;
                CONST[ 7:0] <= CONST_IFDR[7:0];
            end                          
        else if (CONST_ZERO82)
            begin
                CONST[31:9] <= 23'h000000;
                CONST[ 8:1] <= CONST_IFDR[7:0];
                CONST[   0] <= 1'b0;    
            end                          
        else if (CONST_ZERO84)
            begin
                CONST[31:10] <= 22'h000000;
                CONST[ 9: 2] <= CONST_IFDR[7:0];
                CONST[ 1: 0] <= 2'b00;    
            end
        else if (CONST_SIGN8)
            begin
                for (i = 8 ; i <= 31 ; i = i + 1) CONST[i] <= CONST_IFDR[7];
                CONST[ 7:0] <= CONST_IFDR[7:0];
            end
        else if (CONST_SIGN82)
            begin
                for (i = 9 ; i <= 31 ; i = i + 1) CONST[i] <= CONST_IFDR[7];
                CONST[ 8:1] <= CONST_IFDR[7:0];
                CONST[   0] <= 1'b0;
            end
        else if (CONST_SIGN122)
            begin
                for (i = 13 ; i <= 31 ; i = i + 1) CONST[i] <= CONST_IFDR[11];
                CONST[12:1] <= CONST_IFDR[11:0];
                CONST[   0] <= 1'b0;
            end
        else
            CONST[31:0] <= 32'hxxxxxxxx;
    end

//--------------------------
// T value for Bcc judgement
//--------------------------
    always @(T_CMPSET   or CMPRESULT
          or T_CRYSET   or CRYO
          or T_TSTSET   or TSTO
          or T_SFTSET   or SFTO
          or QT_DV1SET  or T_DIV1
          or MQT_DV0SET or T_DIV0S
          or T_CLR
          or T_SET
          or WRSR_Z     or ZBUS
          or WRSR_W     or WBUS
          or SR[`T])
    begin
             if (T_CMPSET)   T_BCC <= CMPRESULT;
        else if (T_CRYSET)   T_BCC <= CRYO;
        else if (T_TSTSET)   T_BCC <= TSTO;
        else if (T_SFTSET)   T_BCC <= SFTO;
        else if (QT_DV1SET)  T_BCC <= T_DIV1;
        else if (MQT_DV0SET) T_BCC <= T_DIV0S;
        else if (T_CLR)      T_BCC <= 1'b0;
        else if (T_SET)      T_BCC <= 1'b1;
        else if (WRSR_W)     T_BCC <= WBUS[0];
        else if (WRSR_Z)     T_BCC <= ZBUS[0];
        else                 T_BCC <= SR[`T];
    end

//----------------
// Status Register
//----------------
    assign IBIT = SR[`I3:`I0];

    always @(posedge CLK)
    begin
        if (RST_SR)
            begin
              //SR[31:16] <= 16'h0000;
              //SR[15:10] <= 6'b000000;
                SR[`I3:`I0] <= 4'b1111;
                SR[3:2] <= 2'b00;
            end
        else if (SLOT)
        begin
            //---------------
            // T bit (bit 0)
            //---------------
            SR[`T] <= T_BCC;
            //--------------
            // Q bit (bit 8)
            //--------------
                 if (QT_DV1SET)  SR[`Q] <= Q_DIV1;
            else if (MQT_DV0SET) SR[`Q] <= XBUS[31];
            else if (MQ_CLR)     SR[`Q] <= 1'b0;
            else if (WRSR_W)     SR[`Q] <= WBUS[8];
            else if (WRSR_Z)     SR[`Q] <= ZBUS[8];
            //--------------
            // M bit (bit 9)
            //--------------
                 if (MQT_DV0SET) SR[`M] <= YBUS[31];
            else if (MQ_CLR)     SR[`M] <= 1'b0;
            else if (WRSR_W)     SR[`M] <= WBUS[9];
            else if (WRSR_Z)     SR[`M] <= ZBUS[9];
            //------
            // I bit
            //------
            if (WR_IBIT)
                SR[`I3:`I0] <= ILEVEL;    
            else if (WRSR_Z)     //ZBUS has the higher priority than WBUS.
                begin
                    SR[`I3:`I0] <= ZBUS[7:4];
                end
            else if (WRSR_W)
                begin
                    SR[`I3:`I0] <= WBUS[7:4];
                end
            //------
            // S bit
            //------
            if (WRSR_Z)     //ZBUS has the higher priority than WBUS.
                begin
                    SR[`S] <= ZBUS[1];
                end
            else if (WRSR_W)
                begin
                    SR[`S] <= WBUS[1];
                end
        end
    end

    always @(posedge CLK)
    begin
        if (MAC_S_LATCH)
            MAC_S <= SR[`S]; 
    end
        
//---------------------
// Global Base Register
//---------------------
    always @(posedge CLK)
    begin
        if (SLOT)
        begin
            if (WRGBR_Z)     //ZBUS has the higher priority than WBUS.
                GBR <= ZBUS;
            else if (WRGBR_W)
                GBR <= WBUS;
        end
    end

//---------------------
// Vector Base Register
//---------------------
    always @(posedge CLK)
    begin
        if (SLOT)
        begin
            if (WRVBR_Z)     //ZBUS has the higher priority than WBUS.
                VBR <= ZBUS;
            else if (WRVBR_W)
                VBR <= WBUS;
        end
    end

//-------------------
// Procedure Register
//-------------------
    always @(posedge CLK)
    begin
        if (SLOT)
        begin
            if (WRPR_PC)
                PR <= PC;
            else if (WRPR_Z)     //ZBUS has the higher priority than WBUS.
                PR <= ZBUS;
            else if (WRPR_W)
                PR <= WBUS;
        end
    end

//-------------------
// Temporary Register
//-------------------
    always @(posedge CLK)
    begin
        if (SLOT)
        begin
            if (WRTEMP_Z)
                TEMP <= ZBUS;
        end
    end

//======================================================
  endmodule
//======================================================