datapath.v

日立SH-2 CPU核的VERLOG源码

//======================================================
// Aquarius Project
//    SuperH-2 ISA Compatible RISC CPU
//------------------------------------------------------
// Module      : Data Path Unit
//------------------------------------------------------
// File        : datapath.v
// Library     : none
// Description : Data Path in CPU.
// Simulator   : Icarus Verilog (Cygwin)
// Synthesizer : Xilinx XST (Windows XP)
// Author      : Thorn Aitch
//------------------------------------------------------
// Revision Number : 1
// Date of Change  : 23rd April 2002
// Creator         : Thorn Aitch
// Description     : Initial Design				  
//------------------------------------------------------
// Revision Number : 2
// Date of Change  : 30th April 2003
// Modifier        : Thorn Aitch
// Description     : Release Version 1.0
//------------------------------------------------------
// Revision Number : 3
// Date of Change  : 10th December 2003
// Modifier        : Thorn Aitch
// Description     : Release Version 1.1
//                   Inhibit substitution of "x"
//                   except for defalut statement whose
//                   case describes all logic spaces. 
//======================================================
// Copyright (C) 2002-2003, Thorn Aitch
//
// Designs can be altered while keeping list of
// modifications "the same as in GNU" No money can
// be earned by selling the designs themselves, but
// anyone can get money by selling the implementation
// of the design, such as ICs based on some cores, 
// boards based on some schematics or Layouts, and
// even GUI interfaces to text mode drivers.
// "The same as GPL SW" Any update to the design
// should be documented and returned to the design. 
// Any derivative work based on the IP should be free
// under OpenIP License. Derivative work means any
// update, change or improvement on the design. 
// Any work based on the design can be either made
// free under OpenIP license or protected by any other
// license. Work based on the design means any work uses
// the OpenIP Licensed core as a building black without
// changing anything on it with any other blocks to
// produce larger design.  There is NO WARRANTY on the
// functionality or performance of the design on the
// real hardware implementation.
// On the other hand, the SuperH-2 ISA (Instruction Set
// Architecture) executed by Aquarius is rigidly
// the property of Renesas Corp. Then you have all 
// responsibility to judge if there are not any 
// infringements to Renesas's rights regarding your 
// Aquarius adoption into your design. 
// By adopting Aquarius, the user assumes all 
// responsibility for its use.
// This project may cause any damages around you, for 
// example, loss of properties, data, money, profits,
// life, or business etc. By adopting this source, 
// the user assumes all responsibility for its use.
//======================================================

`include "timescale.v"
`include "defines.v"

//*************************************************
// Module Definition
//*************************************************
module datapath(
    // system signal
    CLK, RST, SLOT,
    // general register strobe and the number
    RDREG_X,  RDREG_Y,  WRREG_Z,  WRREG_W,
    REGNUM_X, REGNUM_Y, REGNUM_Z, REGNUM_W,
    // ALU function
    ALUFUNC,
    // memory access
    MA_AD,    MA_DW,    MA_DR,
    WRMAAD_Z, WRMADW_X, WRMADW_Y, RDMADR_W,
    // multiplier
    MACIN1, MACIN2,
    MACSEL1, MACSEL2,
    MACH, MACL,
    RDMACH_X, RDMACL_X,
    RDMACH_Y, RDMACL_Y,
    // status register
    RDSR_X, RDSR_Y,
    WRSR_Z, WRSR_W,
    // S bit for MAC
    MAC_S, MAC_S_LATCH,
    // global base register
    RDGBR_X, RDGBR_Y,
    WRGBR_Z, WRGBR_W,
    // vector base register
    RDVBR_X, RDVBR_Y,
    WRVBR_Z, WRVBR_W,
    // procedure register
    RDPR_X, RDPR_Y,
    WRPR_Z, WRPR_W, WRPR_PC,
    // program counter
    RDPC_X, RDPC_Y, WRPC_Z,
    INCPC, IFADSEL, IF_AD,
    // make constant
    CONST_IFDR, 
    CONST_ZERO4, CONST_ZERO42, CONST_ZERO44,                         
    CONST_ZERO8, CONST_ZERO82, CONST_ZERO84,
    CONST_SIGN8, CONST_SIGN82, CONST_SIGN122,
    RDCONST_X, RDCONST_Y,
    // register forward
    REG_FWD_X, REG_FWD_Y,
    // commands for comparator and shifter
    CMPCOM, SFTFUNC,
    // read controls to Z-BUS
    RDSFT_Z, 
    // T value for Bcc judgement
    T_BCC,
    // SR control
    T_CMPSET, T_CRYSET, T_TSTSET, T_SFTSET,
    QT_DV1SET, MQT_DV0SET, T_CLR, T_SET, MQ_CLR,
    // Temporary Register
    RDTEMP_X,
    WRTEMP_Z, WRMAAD_TEMP,
    // I bit in Status Register
    RST_SR, IBIT, ILEVEL, WR_IBIT
    );

//-------------------
// Module I/O Signals
//-------------------
    input  CLK;            // clock
    input  RST;            // reset
    input  SLOT;           // cpu pipe slot

    input  RDREG_X;        // read Rn to X-bus
    input  RDREG_Y;        // read Rn to Y-bus
    input  WRREG_Z;        // write Rn from Z-bus
    input  WRREG_W;        // write Rn from W-bus

    input [3:0] REGNUM_X;  // register number to read to X-bus
    input [3:0] REGNUM_Y;  // register number to read to Y-bus
    input [3:0] REGNUM_Z;  // register number to write from Z-bus
    input [3:0] REGNUM_W;  // register number to write from W-bus

    input  [4:0]  ALUFUNC; // ALU function

    output [31:0] MA_AD;   // memory access address
    output [31:0] MA_DW;   // memory write data
    input  [31:0] MA_DR;   // memory read data
    input  WRMAAD_Z;       // output MA_AD from Z-bus
    input  WRMADW_X;       // output MA_DW from X-bus  
    input  WRMADW_Y;       // output MA_DW from Y-bus
    input  RDMADR_W;       // input MA_DR to W-bus

    output [31:0] MACIN1;  // data1 to mult.v
    output [31:0] MACIN2;  // data2 to mult.v
    input  [1:0] MACSEL1;  // select data of MACIN1 (00:from X, 01:from Z, 1?:from W) 
    input  [1:0] MACSEL2;  // select data of MACIN2 (00:from Y, 01:from Z, 1?:from W) 
    input  [31:0] MACH;    // physical data of MACH
    input  [31:0] MACL;    // physical data of MACL
    input  RDMACH_X;       // read MACH to X-bus
    input  RDMACL_X;       // read MACL to X-bus
    input  RDMACH_Y;       // read MACH to Y-bus
    input  RDMACL_Y;       // read MACL to Y-bus

    input  RDSR_X;         // read SR to X-bus
    input  RDSR_Y;         // read SR to Y-bus
    input  WRSR_Z;         // write SR from Z-bus
    input  WRSR_W;         // write SR from W-bus
    output MAC_S;          // latched S bit in SR (= SR[S])
    input  MAC_S_LATCH;    // latch command of S bit in SR

    input  RDGBR_X;        // read GBR to X-bus
    input  RDGBR_Y;        // read GBR to Y-bus
    input  WRGBR_Z;        // write GBR from Z-bus
    input  WRGBR_W;        // write GBR from W-bus

    input  RDVBR_X;        // read VBR to X-bus
    input  RDVBR_Y;        // read VBR to Y-bus
    input  WRVBR_Z;        // write VBR from Z-bus
    input  WRVBR_W;        // write VBR from W-bus

    input  RDPR_X;         // read PR to X-bus
    input  RDPR_Y;         // read PR to Y-bus
    input  WRPR_Z;         // write PR from Z-bus
    input  WRPR_W;         // write PR from W-bus
    input  WRPR_PC;        // write PR from PC

    input  RDPC_X;         // read PC to X-bus
    input  RDPC_Y;         // read PC to Y-bus
    inout  WRPC_Z;         // write PC from Z-bus
    input  INCPC;          // increment PC (PC+2->PC)
    input  IFADSEL;        // select IF_AD output from INC(0) or Z-bus(1)
    output [31:0] IF_AD;   // instruction fetch address

    input  [15:0] CONST_IFDR;   // instruction fetch data to make constant
    input  CONST_ZERO4;    // take constant from lower 4 bit as unsigned value 
    input  CONST_ZERO42;   // take constant from lower 4 bit as unsigned value * 2
    input  CONST_ZERO44;   // take constant from lower 4 bit as unsigned value * 4
    input  CONST_ZERO8;    // take constant from lower 8 bit as unsigned value
    input  CONST_ZERO82;   // take constant from lower 8 bit as unsigned value * 2
    input  CONST_ZERO84;   // take constant from lower 8 bit as unsigned value * 4
    input  CONST_SIGN8;    // take constant from lower 8 bit as signed value      
    input  CONST_SIGN82;   // take constant from lower 8 bit as signed value * 2
    input  CONST_SIGN122;  // take constant from lower 12 bit as signed value * 2
    input  RDCONST_X;      // read constant to X-bus
    input  RDCONST_Y;      // read constant to Y-bus
    input  REG_FWD_X;      // register forward from W-bus to X-bus
    input  REG_FWD_Y;      // register forward from W-bus to Y-bus

    input  [2:0] CMPCOM;   // define comparator operation (command)
    input  [4:0] SFTFUNC;  // Shifter Function

    input  RDSFT_Z;        // read SFTOUT to Z-BUS

    output T_BCC;          // T value for Bcc judgement
    input  T_CMPSET;       // reflect comparator result to T
    input  T_CRYSET;       // reflect carry/borrow out to T
    input  T_TSTSET;       // reflect tst result to T
    input  T_SFTSET;       // reflect shifted output to T
    input  QT_DV1SET;      // reflect DIV1 result to Q and T
    input  MQT_DV0SET;     // reflect DIV0S result to M, Q and T
    input  T_CLR;          // clear T
    input  T_SET;          // set T
    input  MQ_CLR;         // clear M and Q

    input  RDTEMP_X;       // read TEMP to X-bus
    input  WRTEMP_Z;       // write to TEMP from Z-bus
    input  WRMAAD_TEMP;    // output MAAD from TEMP

    input  RST_SR;         // reset SR
    output [3:0] IBIT;     // I bit in SR
    input  [3:0] ILEVEL;   // IRQ Level
    input  WR_IBIT;        // Write ILEVEL to I bit in SR 

//-----------------
// Internal Signals
//-----------------
    integer i;

    reg  [31:0] XBUS;     // internal X-bus
    reg  [31:0] YBUS;     // internal Y-bus
    reg  [31:0] ZBUS;     // internal Z-bus
    reg  [31:0] WBUS;     // internal W-bus
    reg  [31:0] VBUS;     // internal V-bus

    wire [31:0] REG_X;     // register out toward X
    wire [31:0] REG_Y;     // register out toward Y
    wire [31:0] REG_0;     // R0 value

    reg  [9:0]  SR;        // Status Register
    reg  MAC_S;            // latched S bit in SR

    reg  [31:0] GBR;       // Global Base Register
    reg  [31:0] VBR;       // Vector Base Register
    reg  [31:0] PR;        // Procedure Register

    reg  [31:0] ALUINX;    // ALU internal signal on X-side
    reg  [31:0] ALUINY;    // ALU internal signal on Y-side
    reg  ADDSUB;           // Specify ADD or SUB (ADD=0, SUB=1)
    reg  [32:0] ADDSUBXY;  // Carry :ADDSUBXY = ALUINX + ALUINY + Carry
                           // Borrow:ADDSUBXY = ALUINX - ALUINY - Borrow
    reg  [32:0] ALUINY_EOR;// = ADDSUB ^ ALUINY[]
    reg  [31:0] ALUOUT;    // ALU output
    reg  [31:0] MACIN1;    // data1 to mult.v
    reg  [31:0] MACIN2;    // data2 to mult.v

    reg  [31:0] MA_AD;     // Memory Access Address
    reg  [31:0] MA_DW;     // Memory Write Data
    reg  [31:0] IF_AD;     // Instruction Fetch Address

    reg  [31:0] PC;        // program counter
    reg  [31:0] PCADD2;    // =PC+2

    reg  [31:0] CONST;     // Constant Value generated from Instruction Field

    reg  EQMSB;                  // XBUS[31] == YBUS[31]
    reg  EQHH, EQHL, EQLH, EQLL; // XBUS[n+7:n] == YBUS[n+7:n], n=28,16,8,0
    reg  EQ;                     // XBUS[30:0] == YBUS[30:0]
    reg  HI;                     // XBUS[30:0] > YBUS[30:0]
    reg  CMPRESULT;              // result from comparator according to CMPCOM  
    reg  T_BCC;                  // T value for Bcc judgement

    reg  [31:0] SFTOUT;   // Shifter Output
    reg  SFTO;            // Shifted Output to be sent to T bit
    
    reg  SUBGT, ADDLT;    // Divider internal signal
    reg  Q_DIV1;          // Divider Result of Q by DIV1
    reg  T_DIV1;          // Divider Result of T by DIV1
    reg  T_DIV0S;         // Divider Result of T by DIV0S

    reg  CRYI;   // carry/borrow input to ALU operation
    reg  CRYO;   // carry/borrow output to T
    reg  TSTO;   // test resut to T

    reg  [31:0] R0;    // index register R0 to make MA address; @(R0,Rn)
    reg  [31:0] TEMP ; // Temorary Register

    wire [3:0] IBIT;   // I bit in SR

//----------
// X-BUS
//----------
    always @(WBUS  or REG_FWD_X
          or REG_X or RDREG_X 
          or MACH  or RDMACH_X
          or MACL  or RDMACL_X
          or PC    or RDPC_X
          or CONST or RDCONST_X
          or SR    or RDSR_X
          or GBR   or RDGBR_X
          or VBR   or RDVBR_X
          or PR    or RDPR_X
          or TEMP  or RDTEMP_X)
    begin
        casex ({REG_FWD_X,
                RDREG_X, RDMACH_X, RDMACL_X, RDPC_X, RDCONST_X, 
                RDSR_X, RDGBR_X, RDVBR_X, RDPR_X, RDTEMP_X})
            11'b1?????????? : XBUS <= WBUS;
            11'b01000000000 : XBUS <= REG_X;
            11'b00100000000 : XBUS <= MACH;
            11'b00010000000 : XBUS <= MACL;
            11'b00001000000 : XBUS <= PC;
            11'b00000100000 : XBUS <= CONST;
            11'b00000010000 : XBUS <= {22'h000000, SR};
            11'b00000001000 : XBUS <= GBR;
            11'b00000000100 : XBUS <= VBR;
            11'b00000000010 : XBUS <= PR; 
            11'b00000000001 : XBUS <= TEMP;
            default         : XBUS <= 32'h00000000;
        endcase
    end

//----------
// Y-BUS
//----------
    always @(WBUS  or REG_FWD_Y
          or REG_Y or RDREG_Y
          or MACH  or RDMACH_Y
          or MACL  or RDMACL_Y
          or PC    or RDPC_Y
          or CONST or RDCONST_Y
          or SR    or RDSR_Y 
          or GBR   or RDGBR_Y
          or VBR   or RDVBR_Y
          or PR    or RDPR_Y)
    begin