samples说明.txt

msp430系列单片机样板源代码.rar

MSP-FET430X110 Assembler Examples slac010x.zip (42k) 
fet_1.s43 - Software Toggle P1.0 
fet110_0831.s43 - Software SPI Interface With TLV0831 
fet110_549.s43 - Software SPI Interface TLC549 Set P1.0 if > 0.5*Vcc 
fet110_5616.s43 - Software SPI Interface to TLV5616 12-bit DAC 
fet110_5timers.s43 - 5Timers + 2 Clock Outputs 32kHz ACLK 
fet110_7822.s43 - Software Interface to Read ADS7822 
fet110_ca01.s43 - Comp_A Output Comparator_A reference voltages on P2.3 
fet110_ca02.s43 - Comp_A Detect Theashold, Set P1.0 if P2.3 > 0.25*Vcc 
fet110_ca_temp1.s43 - Comp_A Slope ADC to Detect Temp Level Set P1.0 > 25c 
fet110_ca_temp2.s43 - Comp_A Thermometer 0 - 99 F 
fet110_cd4511.s43 - Software Interface with CD4511 7-Segment Decoder 
fet110_clks.s43 - BasicClock Output buffered SMCLK, ACLK and MCLK/12 
fet110_flash_write.s43 - Flash In-System Programming 
fet110_fll.s43 - BasicClock Implement Auto RSEL SW FLL 
fet110_hc138.s43 - Software Parellel Interface with HC138 
fet110_hc164.s43 - Software SPI Interface with HC164 Shift Register 
fet110_hc165.s43 - Software SPI Interface with HC165 Shift Register 
fet110_hc595.s43 - Software SPI Interface with HC595 Shift Register 
fet110_hfxtal.s43 - BasicClock MCLK configured with HF XTAL 
fet110_int_P2.s43 - Software Port Interrupt Service on P2.0 
fet110_lpm3.s43 - BasicClock LPM3 Using WDT Interrupt, 32kHz ACLK 
fet110_lpm4.s43 - BasicClock LPM4, Pulse P1.0 on P2.0_ISR 
fet110_poll_P2.s43 - Software Poll P2.0, Set P1.0 if P2.0 = 1 
fet110_r2r.s43 - Software Output 6-bit R2R DAC 
fet110_ta_cap01.s43 - Timer_A Ultra-low Power 1200hz detect, ACLK +/- 5% 
fet110_ta_cap02.s43 - Timer_A Ultra-low Power 1800hz detect, SMCLK +/- 1% 
fet110_ta01.s43 - Timer_A Toggle P1.0, CCR0 Contmode ISR, DCO SMCLK 
fet110_ta02.s43 - Timer_A Toggle P1.0, CCR0 upmode ISR, DCO SMCLK 
fet110_ta03.s43 - Timer_A Toggle P1.0, overflow ISR, DCO SMCLK 
fet110_ta04.s43 - Timer_A Toggle P1.0, overflow ISR, 32kHz ACLK 
fet110_ta05.s43 - Timer_A Toggle P1.0, CCR0 upmode ISR, 32kHz ACLK 
fet110_ta06.s43 - Timer_A Toggle P1.0, CCR1 Contmode ISR, DCO SMCLK 
fet110_ta07.s43 - Timer_A Toggle P1.0-3, CCRx Contmode ISR, DCO SMCLK 
fet110_ta08.s43 - Timer_A Toggle P1.0-3, CCRx ISR Contmode, 32kHz ACLK 
fet110_ta09.s43 - Timer_A Toggle P1.0-3, CCRx ISR Contmode, HF XTAL ACLK 
fet110_ta10.s43 - Timer_A Toggle P1.1 With TA0 upmode, DCO SMCLK 
fet110_ta11.s43 - Timer_A Toggle P1.1 With TA0 upmode, 32kHz ACLK 
fet110_ta12.s43 - Timer_A Toggle P1.1 With TA0 upmode, HF XTAL ACLK 
fet110_ta13.s43 - Timer_A Toggle P1.1 With TA0 up-downmode, DCO SMCLK 
fet110_ta14.s43 - Timer_A Toggle P1.1 With TA0 up-downmode, 32kHz ACLK 
fet110_ta15.s43 - Timer_A Toggle P1.1 With TA0 up-downmode, HF XTAL ACLK 
fet110_ta_40k.s43 - Timer_A Output 40khz square wave, UpMode SMCLK DCO 
fet110_ta_pwm01.s43 - Timer_A PWM TA1-2 upmode, DCO SMCLK 
fet110_ta_pwm02.s43 - Timer_A PWM TA1-2 upmode, 32kHz ACLK 
fet110_ta_pwm03.s43 - Timer_A PWM TA1-2 upmode, HFTAL ACLK 
fet110_ta_pwm04.s43 - Timer_A PWM TA1-2 up-downmode, DCO SMCLK 
fet110_ta_pwm05.s43 - Timer_A PWM TA1-2 up-downmode, 32kHz ACLK 
fet110_ta_pwm06.s43 - Timer_A PWM TA1-2 up-downmode, HFTAL ACLK 
fet110_ta_uart2400.s43 - Timer_A UART 2400 Ultra-low Power Echo, 32kHz ACLK 
fet110_ta_uart9600.s43 - Timer_A UART 9600 Echo, HF XTAL ACLK 
fet110_ta_uart115k.s43 - Timer_A UART 115200 Echo, HF XTAL ACLK 
fet110_wdt01.s43 - WDT Toggle P1.0 Interval overflow ISR, DCO SMCLK 
fet110_wdt02.s43 - WDT Toggle P1.0 Interval overflow ISR, 32kHz ACLK 
fet110_wdt03.s43 - WDT Toggle P1.0 Interval overflow ISR, HF XTAL ACLK 


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MSP-FET430X110 "C" Examples slac011x.zip  (35k) 
fet_1.c - Software Toggle P1.0 
fet110_549 - Software SPI Interface TLC549 Set P1.0 if > 0.5*Vcc 
fet110_ca01.c - Comp_A Output Comparator_A reference voltages on P2.3 
fet110_ca02.c - Comp_A Detect theashold, Set P1.0 if P2.3 > 0.25*Vcc 
fet110_clks.c - BasicClock Output buffered SMCLK, ACLK and MCLK/12 
fet110_flash_write.c - Flash In-System Programming 
fet110_fll.c - BasicClock Implement Auto RSEL SW FLL 
fet110_hfxtal.c - BasicClock MCLK configured with HF XTAL 
fet110_lpm3.c - BasicClock LPM3 Using WDT ISR, 32kHz ACLK 
fet110_ta01.c - Timer_A Toggle P1.0, CCR0 Contmode ISR, DCO SMCLK 
fet110_ta02.c - Timer_A Toggle P1.0, CCR0 upmode ISR, DCO SMCLK 
fet110_ta03.c - Timer_A Toggle P1.0, overflow ISR, DCO SMCLK 
fet110_ta04.c - Timer_A Toggle P1.0, overflow ISR, 32kHz ACLK 
fet110_ta05.c - Timer_A Toggle P1.0, CCR0 upmode ISR, 32kHz ACLK 
fet110_ta06.c - Timer_A Toggle P1.0, CCR1 Contmode ISR, DCO SMCLK 
fet110_ta07.c - Timer_A Toggle P1.0-3 CCRx Contmode ISR, DCO SMCLK 
fet110_ta08.c - Timer_A Toggle P1.0-3 CCRx Contmode ISR, 32kHz ACLK 
fet110_ta09.c - Timer_A Toggle P1.0-3 CCRx Contmode ISR, HF XTAL ACLK 
fet110_ta10.c - Timer_A Toggle P1.1 With TA0 upmode, DCO SMCLK 
fet110_ta11.c - Timer_A Toggle P1.1 With TA0 upmode, 32kHz ACLK 
fet110_ta12.c - Timer_A Toggle P1.1 With TA0 upmode, HF XTAL ACLK 
fet110_ta13.c - Timer_A Toggle P1.1 With TA0 up-downmode, DCO SMCLK 
fet110_ta14.c - Timer_A Toggle P1.1 With TA0 up-downmode, 32kHz ACLK 
fet110_ta15.c - Timer_A Toggle P1.1 With TA0 up-downmode, HF XTAL ACLK 
fet110_ta_pwm01.c - Timer_A PWM TA1-2 upmode, DCO SMCLK 
fet110_ta_pwm02.c - Timer_A PWM TA1-2 upmode, 32kHz ACLK 
fet110_ta_pwm03.c - Timer_A PWM TA1-2 upmode, HFTAL ACLK 
fet110_ta_pwm04.c - Timer_A PWM TA1-2 up-downmode, DCO SMCLK 
fet110_ta_pwm05.c - Timer_A PWM TA1-2 up-downmode, 32kHz ACLK 
fet110_ta_pwm06.c - Timer_A PWM TA1-2 up-downmode, HFTAL ACLK 
fet110_ta_uart2400.c - Timer_A UART 2400 Ultra-low Power Echo, 32kHz ACLK 
fet110_ta_uart9600.c - Timer_A UART 9600 Echo, HF XTAL ACLK 
fet110_ta_uart115k.c - Timer_A UART 115200 Echo, HF XTAL ACLK 
fet110_wdt01.c - WDT Toggle P1.0 Interval overflow ISR, DCO SMCLK 
fet110_wdt02.c - WDT Toggle P1.0 Interval overflow ISR, 32kHz ACLK 


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MSP-FET430P120 Assembler Examples slac012x.zip  (24k) 
fet120_1.s43 - Software Toggle P1.0 
fet120_5timers.s43 - 5Timers + 2 Clock Outputs 32kHz ACLK 
fet120_7822.s43 - Software Interface to Read ADS7822 
fet120_ADC10_00.s43 - ADC10 Sample A0, AVcc 
fet120_ADC10_01.s43 - ADC10 Sample A0, AVcc, Set P1.0 if A0 > 0.5*AVcc 
fet120_ADC10_02.s43 - ADC10 Sample A0, 1.5V, Set P1.0 if A0 > 0.2V 
fet120_ADC10_03.s43 - ADC10 Sample A10 Temp Set P1.0 if temp > ~ 29c 
fet120_ADC10_04.s43 - ADC10 Sample A0 Signed AVcc Set P1.0 if A0 > 0.5*AVcc 
fet120_ADC10_05.s43 - ADC10 Sample A11 lo_Batt Set P1.0 if < 2.3V 
fet120_ADC10_06.s43 - ADC10 Output Internal Vref on P2.4 and Osc. on P1.0 
fet120_ADC10_07.s43 - ADC10 Sample A0 64x, AVcc, Repeat Single DTC DCO 
fet120_ADC10_08.s43 - ADC10 Sample A0 64x, 1.5V, Repeat Single DTC DCO 
fet120_ADC10_09.s43 - ADC10 Sample A10 64x, 1.5V, Repeat Single DTC DCO 
fet120_ADC10_10.s43 - ADC10 Sample A2-0, AVcc, Single Sequence DTC DCO 
fet120_ADC10_11.s43 - ADC10 Sample A0, 1.5V, TA1 Trigger Set P1.0 if > 0.5V 
fet120_ADC10_12.s43 - ADC10 Sample A7, 1.5V, TA1 Trigger Ultra-low Power 
fet120_ADC10_13.s43 - ADC10 Sample A1 32x, AVcc, TA1 Trigger, DTC DCO 
fet120_ADC10_14.s43 - ADC10 Sample A1-0 32x, AVcc, Repeat Sequence, DTC DCO 
fet120_ADC10_15.s43 - ADC10 Sample A0 -> TA1, AVcc, DTC DCO 
fet120_ADC10_16.s43 - ADC10 Sample A0 -> TA1 ContMode, AVcc, DTC HF XTAL 
fet120_ADC10_17.s43 - ADC10 Sample A1-0 -> TA1/2 ContMode, 2.5V, DTC HF XTAL 
fet120_ADC10_18.s43 - ADC10 Sample A10 32x Directly to Flash, AVcc, DTC DCO 
fet120_ADC10_19.s43 - ADC10 Sample A0 64x, AVcc, DTC HF XTAL 
fet120_ADC10_20.s43 - ADC10 Sample A0 2-Block ContMode, DTC HF XTAL 
fet120_ADC10_temp.s43 - ADC10 Sample A10 Temp and Convert to oC and oF 
fet120_clks.s43 - BasicClock Output buffered SMCLK, ACLK and MCLK/12 
fet120_fll2.s43 - BasicClock Implement Continous SW FLL with Auto RSEL 
fet120_hfxtal.s43 - BasicClock LFXT1/MCLK configured with HF XTAL 
fet120_hfxtal_nmi.s43 - BasicClock LFXT1/MCLK configured with HF XTAL and NMI 
fet120_lpm3.s43 - BasicClock LPM3 Using WDT Interrupt ISR, 32kHz ACLK 
fet120_nmi.s43 - BasicClock Configure RST/NMI as NMI 
fet120_rosc.s43 - BasicClock DCOCLK Biased with External Resistor Rosc 
fet120_spi0_016x.s43 - USART0 SPI Interface to HC165/164 Shift Registers 
fet120_spi0_0549.s43 - USART0 SPI Interface to TLC549 8-bit ADC 
fet120_spi0_7822.s43 - USART0 SPI Interface to ADS7822 ADC 
fet120_ta01.s43 - Timer_A Toggle P1.0, CCR0 Contmode ISR, DCO SMCLK 
fet120_ta02.s43 - Timer_A Toggle P1.0, CCR0 upmode ISR, DCO SMCLK 
fet120_ta03.s43 - Timer_A Toggle P1.0, overflow ISR, DCO SMCLK 
fet120_ta04.s43 - Timer_A Toggle P1.0, overflow ISR, 32kHz ACLK 
fet120_ta05.s43 - Timer_A Toggle P1.0, CCR0 upmode ISR, 32kHz ACLK 
fet120_ta06.s43 - Timer_A Toggle P1.0, CCR1 Contmode ISR, DCO SMCLK 
fet120_ta07.s43 - Timer_A Toggle P1.0-3, CCRx Contmode ISR, DCO SMCLK 
fet120_ta08.s43 - Timer_A Toggle P1.0-3, CCRx Contmode ISR, 32kHz ACLK 
fet120_ta09.s43 - Timer_A Toggle P1.0-3, CCRx Contmode ISR, HF XTAL ACLK 
fet120_ta10.s43 - Timer_A Toggle P1.1 With TA0 upmode, DCO SMCLK 
fet120_ta11.s43 - Timer_A Toggle P1.1 With TA0 upmode, 32kHz ACLK 
fet120_ta12.s43 - Timer_A Toggle P1.1 With TA0 upmode, HF XTAL ACLK 
fet120_ta13.s43 - Timer_A Toggle P1.1 With TA0 up-downmode, DCO SMCLK 
fet120_ta14.s43 - Timer_A Toggle P1.1 With TA0 up-downmode, 32kHz ACLK 
fet120_ta15.s43 - Timer_A Toggle P1.1 With TA0 up-downmode, HF XTAL ACLK 
fet120_ta_count.s43 - Timer_A Used as Ultra-low Power Pulse Accumulator 
fet120_ta_pwm01.s43 - Timer_A PWM TA1-2 upmode, DCO SMCLK 
fet120_ta_pwm02.s43 - Timer_A PWM TA1-2 upmode, 32kHz ACLK 
fet120_ta_pwm03.s43 - Timer_A PWM TA1-2 upmode, HFTAL ACLK 
fet120_ta_pwm04.s43 - Timer_A PWM TA1-2 up-downmode, DCO SMCLK 
fet120_ta_pwm05.s43 - Timer_A PWM TA1-2 up-downmode, 32kHz ACLK 
fet120_ta_pwm06.s43 - Timer_A PWM TA1-2 up-downmode, HFTAL ACLK 
fet120_uart01_02400.s43 - USART0 UART 2400 Ultra-low Power Echo ISR, 32kHz ACLK 
fet120_uart01_09600.s43 - USART0 UART 9600 Echo ISR, HF XTAL ACCLK 
fet120_uart01_19200.s43 - USART0 UART 19200 Echo ISR, HF XTAL ACLK 
fet120_uart02_19200.s43 - USART0 UART 19200 Ultra-low Echo ISR, 32kHz ACLK + DCO 
fet120_uart03_19200.s43 - USART0 UART 19200 Echo ISR, 32kHz ACLK + DCO 
fet120_uart01_0115k.s43 - USART0 UART 115200 Echo ISR, HF XTAL ACLK 
fet120_wdt01.s43 - WDT Toggle P1.0 Interval overflow ISR, DCO SMCLK 
fet120_wdt02.s43 - WDT Toggle P1.0 Interval overflow ISR, 32kHz ACLK 
fet120_wdt03.s43 - WDT Toggle P1.0 Interval overflow ISR, HF XTAL ACLK 



 

 
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MSP-FET430P120 "C" Examples slac013x.zip  (24k) 
fet120_1.c - Software Toggle P1.0 
fet120_ADC10_01.c - ADC10 Sample A0, AVcc, Set P1.0 if > 0.5*AVcc 
fet120_ADC10_02.c - ADC10 Sample A0, 1.5V, Set P1.0 if > 0.2V 
fet120_ADC10_03.c - ADC10 Sample A10 Temp Set P1.0 if temp > ~ 29c 
fet120_ADC10_04.c - ADC10 Sample A0 Signed AVcc Set P1.0 if > 0.5*AVcc 
fet120_ADC10_05.c - ADC10 Sample A11 lo_Batt Set P1.0 if < 2.3V 
fet120_ADC10_06.c - ADC10 Output Internal Vref on P2.4 and Osc. on P1.0 
fet120_ADC10_07.c - ADC10 Sample A0 64x, AVcc, Repeat Single DTC DCO 
fet120_ADC10_08.c - ADC10 Sample A0 64x, 1.5V, Repeat Single DTC DCO 
fet120_ADC10_09.c - ADC10 Sample A10 64x, 1.5v, Repeat Single DTC DCO 
fet120_ADC10_10.c - ADC10 Sample A2-0, AVcc, SIngle Sequence DTC DCO 
fet120_ADC10_temp.c - ADC10 Sample A10Temp and Convert to oC and oF 
fet120_clks.c - BasicClock Output buffered SMCLK, ACLK and MCLK/12 
fet120_flash_write.c - Flash In-System Programming 
fet120_hfxtal.c - BasicClock MCLK configured with HF XTAL 
fet120_lpm3.c - BasicClock LPM3 Using WDT ISR, 32kHz ACLK 
fet120_spi0_016x.c - USART0 SPI Interface with HC165/164 Shift Registers 
fet120_ta01.c - Timer_A Toggle P1.0, CCR0 Contmode ISR, DCO SMCLK 
fet120_ta02.c - Timer_A Toggle P1.0, CCR0 upmode ISR, DCO SMCLK 
fet120_ta03.c - Timer_A Toggle P1.0, overflow ISR, DCO SMCLK 
fet120_ta04.c - Timer_A Toggle P1.0, overflow ISR, 32kHz ACLK 
fet120_ta05.c - Timer_A Toggle P1.0, CCR0 upmode ISR, 32kHz ACLK 
fet120_ta06.c - Timer_A Toggle P1.0, CCR1 Contmode ISR, DCO SMCLK 
fet120_ta07.c - Timer_A Toggle P1.0-3 CCRx Contmode ISR, DCO SMCLK 
fet120_ta08.c - Timer_A Toggle P1.0-3 CCRx Contmode ISR, 32kHz ACLK 
fet120_ta09.c - Timer_A Toggle P1.0-3 CCRx Contmode ISR, HF XTAL ACLK 
fet120_ta10.c - Timer_A Toggle P1.1 With TA0 upmode, DCO SMCLK 
fet120_ta11.c - Timer_A Toggle P1.1 With TA0 upmode, 32kHz ACLK 
fet120_ta12.c - Timer_A Toggle P1.1 With TA0 upmode, HF XTAL ACLK 
fet120_ta13.c - Timer_A Toggle P1.1 With TA0 up-downmode, DCO SMCLK 
fet120_ta14.c - Timer_A Toggle P1.1 With TA0 up-downmode, 32kHz ACLK 
fet120_ta15.c - Timer_A Toggle P1.1 With TA0 up-downmode, HF XTAL ACLK 
fet120_ta_pwm01.c - Timer_A PWM TA1-2 upmode, DCO SMCLK 
fet120_ta_pwm02.c - Timer_A PWM TA1-2 upmode, 32kHz ACLK 
fet120_ta_pwm03.c - Timer_A PWM TA1-2 upmode, HFTAL ACLK 
fet120_ta_pwm04.c - Timer_A PWM TA1-2 up-downmode, DCO SMCLK 
fet120_ta_pwm05.c - Timer_A PWM TA1-2 up-downmode, 32kHz ACLK 
fet120_ta_pwm06.c - Timer_A PWM TA1-2 up-downmode, HFTAL ACLK 
fet120_uart01_02400.c - USART0 UART 2400 Ultra-low Power Echo ISR, 32kHz ACLK 
fet120_uart01_09600.c - USART0 UART 9600 Echo ISR, HF XTAL ACLK 
fet120_uart01_19200.c - USART0 UART 19200 Echo ISR, HF XTAL ACLK 
fet120_uart01_0115k.c - USART0 UART 115200 Echo ISR, HF XTAL ACLK 
fet120_wdt01.c - WDT Toggle P1.0 Interval overflow ISR, DCO SMCLK 
fet120_wdt02.c - WDT Toggle P1.0 Interval overflow ISR, 32kHz ACLK 
fet120_wdt03.c - WDT Toggle P1.0 Interval overflow ISR, HF XTAL ACLK 


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MSP-FET430P140 Assembler Examples slac014x.zip  (38k) 
fet140_1.s43 - Software Toggle P1.0 
fet140_adc12_00.s43 - ADC12 Sample A0, AVcc 
fet140_adc12_01.s43 - ADC12 Using 10 External Channels for Conversion 
fet140_adc12_02.s43 - ADC12 Using an External Reference 
fet140_adc12_03.s43 - ADC12 Extended sampling 
fet140_adc12_04.s43 - ADC12 Using the Internal Reference 
fet140_adc12_05.s43 - ADC12 Repeated Sequence of Conversions 
fet140_adc12_06.s43 - ADC12 Repeated Single Channel Conversions 
fet140_adc12_07.s43 - ADC12 Single Conversion on Single Channel 
fet140_adc12_08.s43 - ADC12 Sequence of Conversions (non-repeated) 
fet140_adc12_09.s43 - ADC12 Using the temperature diode 
fet140_adc12_10.s43 - ADC12, Trigger Conversion With Timer_A 
fet140_clks.s43 - BasicClock Output buffered SMCLK, ACLK and MCLK 
fet140_hfxt2.s43 - BasicClock MCLK configured with HF XTAL XT2 
fet140_hfxtal.s43 - BasicClock LFXT1/MCLK configured with HF XTAL 
fet140_hfxtal_nmi.s43 - BasicClock MCLK configured with HF XTAL and OscFault 
fet140_lpm3.s43 - BasicClock LPM3 Using WDT Interrupt ISR, 32kHz ACLK 
fet140_spi0_0164.s43 - USART0 SPI Interface to HC164 Shift Register 
fet140_spi0_0165.s43 - USART0 SPI Interface to HC165 Shift Register 
fet140_spi0_016x.s43 - USART0 SPI Interface to HC165/164 Shift Registers 
fet140_spi0_0549.s43 - USART0 SPI Interface to TLC549 8-bit ADC 
fet140_spi0_5616.s43 - USART0 SPI Interface to TLV5516 DAC 
fet140_ta_pwm01.s43 - Timer_A PWM TA1-2 upmode, DCO SMCLK 
fet140_ta_pwm02.s43 - Timer_A PWM TA1-2 upmode, 32kHz ACLK 
fet140_ta_pwm03.s43 - Timer_A PWM TA1-2 upmode, HFTAL ACLK 
fet140_ta_pwm04.s43 - Timer_A PWM TA1-2 up-downmode, DCO SMCLK