📄 sy13.a30
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;****************************************************************
;* *
;* SAMPLE PROGRAM : 1 SEC COUNTER *
;* FILE NAME : SAMP1a.A30 *
;* FUNCTION : SW1 => COUNTER START or stop *
;* *
;* SW3 => COUNTER CLEAR *
;* *
;****************************************************************
;
; Copyright,1999
; MITSUBISHI ERECTRIC CORPORATION AND
; MITSUBISHI ERECTRIC SEMICONDUCTOR SOFTWARE CORPORATIOON
;
;---------- INCLUDE OF SFR FILE ----------
;
.list off ; don't draw up a prpgram list
.include sfr62s.inc ; include of sfr file
.list on ; draw up a program list
;
;---------- DEFINE OF SYMBOLS ----------
;
VramTOP .equ 000400H ; top address of internal RAM
VramEND .equ 002BFFH ; end address of internal RAM
VIstack .equ 002C00H ; stack pointer
VprogTOP .equ 0F0000H ; top address of program area
Vintbase .equ 0FA000H ; top address of variable vector table
Vvector .equ 0FFFDCH ; top address of fixed vector table
SB_base .equ 000380H ; base address of SB recative
;
;---------- KEEP OF RAM AREA ----------
;
.section memory,data
.org VramTOP
;
LED: .blkb 2 ; LED display data
Tsec: .blkb 1 ; sec buffer
Fdig: .blkb 1
sw_in: .blkb 1 ; start-stop buffer
cnt_clr: .blkb 1 ; count clear buffer
;
.section prog,code
.org VprogTOP
.sb SB_base ; assings aprovisional SB register value
.sbsym LED ; place data in SB addressing mode
.sbsym Tsec ; place data in SB addressing mode
.sbsym Fdig ; place data in SB addressing mode
;
;---------- CLEAR OF RAM ----------
;
reset:
ldc #VIstack,ISP ; set Interrupt Stack Pointer
ldc #SB_base,SB ; set SB register
; ldintb #Vintbase ; set Interrupt TaBle register
;
mov.w #0,r0 ; 0 clear
mov.w #(VramEND+1-VramTOP)/2,r3 ; number of times
mov.w #VramTOP,a1 ; start address
sstr.w
;
;---------- INITIALLIZE ----------
;
LDINTB #USER_vector_table
mov.w #0FFFFH,pd0 ; P0,P1 output set
;
mov.b #00000110B,adic ; A-D Interrupt control reg set
mov.b #00000110B,int0ic ; INT0 Interrupt control reg set
mov.b #00000110B,int1ic ; INT1 Interrupt control reg set
mov.b #00000000B,ta0ic ; TIMER A0 Interrupt control reg set
mov.b #80H,ta0mr ; f1*32 = 2 usec
mov.w #1000,ta0 ; make 2 msec
bset ta0s ; TIMER A0 start
fset i
;---------- A-D CONVERTER ----------
mov.b #01H,adcon2 ; A-D register 2
mov.b #0A0H,adcon0 ; A-D register 0
mov.b #20H,adcon1 ; A-D register 1
bset adst ; A-D conversion start
;
;---------- MAIN PROGRAM ----------
;
main:
mov.w #50,r0 ; 50 => r0
check:
btstc 3,ta0ic ; 2 msec?
jnc check ; return
jsr display ; subroutine display
sbjnz.w #1,r0,check ; 0.1sec?
jsr timer ; subroutine timer
jmp main
delay:
mov.w #50,r1
loop: sbjnz.w #1,r1,loop
rts
;
;---------- SWITCH CHECK ----------
;
sw_int1:
;========== start ==========
fset i
jsr delay
btst 3,p8
jc sw1
cmp.b #1,sw_in
stzx #0,#1,sw_in ;sw_in=sw_in xor 1
mov.b #0,cnt_clr ; sw_in flag clear
sw1: reit
sw_int0:
reit
sw_adtrg:
;========== clear ==========
fset i
mov.b #1,cnt_clr ; timer count flag on
reit
;
;---------- TIMER COUNT ----------
;
timer:
push.b r0l
cmp.b #1,sw_in ; sw_in - 1(start?)
jnz timer_end ; jump not ZERO
mov.b Tsec,r0l ; Tsec => r0l
dadd.b #1,r0l ; 1sec count up
mov.b r0l,Tsec ; r0l => Tsec
cmp.b #1,cnt_clr
stz #00,Tsec
stz #0,sw_in ; sw_in flag clear(stop)
mov.b Tsec,r0l ; Tsec => r0l
movll r0l,LED ; r0l => LED(low => low)
movhl r0l,LED+1 ; r0l => LED+1(hight => low)
timer_end:
cmp.b #1,cnt_clr
stz #00,Tsec
stz #0,sw_in ; sw_in flag clear(stop)
mov.b Tsec,r0l ; Tsec => r0l
movll r0l,LED ; r0l => LED(low => low)
movhl r0l,LED+1 ; r0l => LED+1(hight => low)
pop.b r0l
rts
;
;---------- LED DISPLAY ----------
;
display:
push.w a0
mov.b #0FFH,p0 ; turn off LED
add.b #1,Fdig ; digit flag count up
cmp.b #2,Fdig ; Fdig=4?
stz #0,Fdig ; Fdig clear at r0l=4
mov.b Fdig,a0 ; Fdig => a0
mov.b LED[a0],a0
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
cmp.b #0,Fdig
jnz LED1 ; display data read
lde.b LED_data[a0],p0
jmp haha
LED1: lde.b LED_data1[a0],p0 ;带小数点 ; P0 output
haha: mov.b Fdig,a0 ; Fdig => a0
lde.b Digit_data[a0],p1 ; P1 output
pop.w a0
rts
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
LED_data:
.byte 0C0H,0F9H,0A4H,0B0H,099H ;0,1,2,3,4
.byte 092H,082H,0F8H,080H,098H ;5,6,7,8,9
LED_data1:
.byte 0C0H-80H,0F9H-80H,0A4H-80H,0B0H-80H,099H-80H ;0,1,2,3,4
.byte 092H-80H,082H-80H,0F8H-80H,080H-80H,098H-80H
Digit_data:
.byte 0FDH,0FEH ;1,2digit
;---------- DUMMY UART0 INTERRUPT PROGRAM ----------
dummy:
reit
;---------- VARIABLE VECTOR TABLE SET ----------
;
.section val_vect,romdata
.org Vintbase
USER_vector_table:
.lword dummy ; No0 Break Interrupt
.lword dummy ; No1 Break Interrupt
.lword dummy ; No2 Break Interrupt
.lword dummy ; No3 Break Interrupt
.lword dummy ; No4 Break Interrupt
.lword dummy ; No5 Break Interrupt
.lword dummy ; No6 Break Interrupt
.lword dummy ; No7 Break Interrupt
.lword dummy ; No8 Break Interrupt
.lword dummy ; No9 Break Interrupt
.lword dummy ; No10 Bus Clash Detect
.lword dummy ; No11 DMA0
.lword dummy ; No12 DMA1
.lword dummy ; No13 KEY IN Interrupt
.lword sw_adtrg ; No14 A-D Interrupt
.lword dummy ; No15 UART2 Transmission Interrupt
.lword dummy ; No16 UART2 receive Interrupt
.lword dummy ; No17 UART0 Transmission Interrupt
.lword dummy ; No18 UART0 receive Interrupt
.lword 0FCB6BH ; No19 UART1 Transmission Interrupt
.lword 0FCB6BH ; No20 UART1 receive Interrupt
.lword dummy ; No21 TimerA0 Interrupt
.lword dummy ; No22 TimerA1 Interrupt
.lword dummy ; No23 TimerA2 Interrupt
.lword dummy ; No24 TimerA3 Interrupt
.lword dummy ; No25 TimerA4 Interrupt
.lword dummy ; No26 TimerB0 Interrupt
.lword dummy ; No27 TimerB1 Interrupt
.lword dummy ; No28 TimerB2 Interrupt
.lword sw_int0 ; No29 INIT0(Active Low) Interrupt
.lword sw_int1 ; No30 INIT1(Active Low) Interrupt
.lword dummy ; No31 INIT2(Active Low) Interrupt
.lword dummy ; No32 S/W Interrupt
.lword dummy ; No33 S/W Interrupt
.lword dummy ; No34 S/W Interrupt
.lword dummy ; No35 S/W Interrupt
.lword dummy ; No36 S/W Interrupt
.lword dummy ; No37 S/W Interrupt
.lword dummy ; No38 S/W Interrupt
.lword dummy ; No39 S/W Interrupt
.lword dummy ; No40 S/W Interrupt
.lword dummy ; No41 S/W Interrupt
.lword dummy ; No42 S/W Interrupt
.lword dummy ; No43 S/W Interrupt
.lword dummy ; No44 S/W Interrupt
.lword dummy ; No45 S/W Interrupt
.lword dummy ; No46 S/W Interrupt
.lword dummy ; No47 S/W Interrupt
.lword dummy ; No48 S/W Interrupt
.lword dummy ; No49 S/W Interrupt
.lword dummy ; No50 S/W Interrupt
.lword dummy ; No51 S/W Interrupt
.lword dummy ; No52 S/W Interrupt
.lword dummy ; No53 S/W Interrupt
.lword dummy ; No54 S/W Interrupt
.lword dummy ; No55 S/W Interrupt
.lword dummy ; No56 S/W Interrupt
.lword dummy ; No57 S/W Interrupt
.lword dummy ; No58 S/W Interrupt
.lword dummy ; No59 S/W Interrupt
.lword dummy ; No60 S/W Interrupt
.lword dummy ; No61 S/W Interrupt
.lword dummy ; No62 S/W Interrupt
.lword dummy ; No63 S/W Interrupt
;
;---------- VECTOR TABLE ----------
;
.section inter,romdata
.org Vvector+(8*4)
.lword reset
;
;---------- PROGRAM END ----------
;
.end
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