📄 3_vf_main.asm
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; call pjsf
; bcnd sfjx,neq
mar *,ar2 ;
lar ar2,#200h ;change the display speed
ysjg
KICK_DOG
call delay_time
banz ysjg
B turn1 ; End of background loop
;------------------the serial_comm main loop---------------------------------
comm_loop ;计算机控制
ldp #04h
splk #0h,add_var
splk #0h,add_cen
splk #0h,sub_var
call _ci
LACL SCIRXBUF ; else, load ACCL with character received
AND #00FFh ; mask unsignificant bits in ACC
ldp #4
sacl start_key
lacl start_key
sub #1fh
bcnd vv_con,neq
SPLK #0fH,LED2
SPLK #1H,LED3
SETC INTM
CALL DIS
CLRC INTM
call _co ; Send the same value to the PC
ldp #04h
lacl start_key
LDP #0E0H
SACL SCITXBUF
vv_con
ldp #04h ;if recesive #00h,then jump to the main_loop
lacl start_key
sub #2fh
bcnd sv_con,neq
SPLK #0fH,LED2
SPLK #2H,LED3
SETC INTM
CALL DIS
CLRC INTM
call _co ; Send the same value to the PC
ldp #04h
lacl start_key
LDP #0E0H
SACL SCITXBUF
sv_con
ldp #04h ;if recesive #00h,then jump to the main_loop
lacl start_key
sub #3fh
bcnd start_on,neq
SPLK #0fH,LED2
SPLK #3H,LED3
SETC INTM
CALL DIS
CLRC INTM
call _co ; Send the same value to the PC
ldp #04h
lacl start_key
LDP #0E0H
SACL SCITXBUF
start_on
ldp #04h ;if recesive #00h,then jump to the main_loop
lacl start_key
sub #3eh
bcnd key_con,neq
call _co ; Send the same value to the PC
ldp #04h
lacl start_key
LDP #0E0H
SACL SCITXBUF
B start_loop
key_con
ldp #04h ;if recesive #00h,then jump to the main_loop
lacl start_key
sub #00h
bcnd comm_loop,neq
call _co ; Send the same value to the PC
ldp #04h
lacl start_key
LDP #0E0H
SACL SCITXBUF
b key_control
;--------------------------------------------------------------------------------
;--------------------------------------------------------------------------------
start_loop ;start key
form1
ldp #04h
lacl LED3
sub #01h
bcnd form2,neq
b spwm
form2
lacl LED3
sub #02h
bcnd form3,neq
b vvpwm
form3
b svpwm
spwm
call spwm_ini_pwm
call spwm_main
call spwm_start
splk #stable,toptable
clrc intm
b comm_body
;----------------------------------------------------------------------------------
vvpwm
call spwm_ini_pwm
call spwm_main
call spwm_start
splk #vvpwm_stable,toptable
clrc intm
b comm_body
;----------------------------------------------------------------------------------
svpwm
call svpwm_ini_pwm
call svpwm_varies_ini
call svpwm_start
clrc intm
b comm_body
comm_body
ldp #04H
SPLK #0H,LED0
SPLK #0H,LED1
; SPLK #0fH,LED2
; SPLK #1H,LED3
SETC INTM
CALL DIS
CLRC INTM
start_loop1
call _ci
lacl SCIRXBUF
and #00ffh ;only 8 bits !!!
ldp #04h ;if yes, get it and store it in option
sacl option
lacl option
sub #0ffh ;(PC<-->02H)
bcnd notstop_key,neq
call _co
ldp #04h
lacl option
LDP #0E0H
SACL SCITXBUF
;-------------------------------------------------------------------------------
stop_key
ldp #04h ;point to variables
splk #0,count_h
splk #0,count_l
SPLK #0FH,LED0
SPLK #0FH,LED1
SPLK #0FH,LED2
SPLK #01H,LED3
SETC INTM
CALL DIS
CLRC INTM
b comm_loop
;-------------------------------------------------------------------------------
notstop_key
ldp #04h
lacc option
sub #33h ;(<PC-->03H)
bcnd notadd_key,neq
call _co
ldp #04h
lacl option
LDP #0E0H
SACL SCITXBUF
;-------------------------------------------------------------------------------
add_key ;add key
setc intm
ldp #04h
lacl add_var
add #1
sacl add_var
sacl add_temp
call hex_bcd
ldp #04h
lacl add_var_h
sub #06h
bcnd yichu,geq
lacl add_var_h
sacl LED1
lacl add_var_l
sacl LED0
add_xun
lacl LED0
sacl count_l
lacl LED1
sacl count_h
CALL DIS
clrc intm
B start_loop1
yichu
splk #06h,LED1
splk #00h,LED0
splk #60,add_var
b add_xun
;--------------------------------------------------------------------------------
notadd_key
ldp #04h
lacc option
sub #34h ;(PC<-->04H)
bcnd notsub_key,neq
call _co
ldp #04h
lacl option
LDP #0E0H
SACL SCITXBUF
;--------------------------------------------------------------------------------
sub_key ;substract key
setc intm
ldp #04h
lacl add_var
sub #00h
bcnd sub_yichu,eq
sub #01h
sacl add_var
sacl add_temp
call hex_bcd
lacl add_var_l
sub #0
bcnd sub_yichu,lt
lacl add_var_h
sacl LED1
lacl add_var_l
sacl LED0
sub_xun
lacl LED0
sacl count_l
lacl LED1
sacl count_h
CALL DIS
clrc intm
B start_loop1
sub_yichu
splk #00h,LED0
splk #00h,LED1
splk #00h,add_var
b sub_xun
;-------------------------------------------------------------------------------
notsub_key
ldp #04h
lacc option
sub #80h ;(PC<-->04H)
bcnd nottrans_key,neq
call _co
ldp #04h
lacl option
LDP #0E0H
SACL SCITXBUF
trans_key
call _ci
lacl SCIRXBUF
and #00ffh ;only 8 bits !!!
ldp #04h
sacl add_var
sacl add_temp
call hex_bcd
ldp #04h
lacl add_var_h
sacl LED1
lacl add_var_l
sacl LED0
lacl LED0
sacl count_l
lacl LED1
sacl count_h
SETC INTM
CALL DIS
CLRC INTM
call _co
ldp #04h
lacl add_var
LDP #0E0H
SACL SCITXBUF
b start_loop1
nottrans_key
ldp #04h
lacc option
sub #71h
bcnd notspwm_comp_key,neq
call _co
ldp #04h
lacl option
LDP #0E0H
SACL SCITXBUF
spwm_comp_key
call _ci
lacl SCIRXBUF
and #00ffh
ldp #04h
sacl vf_spwm_varl
call _co
ldp #04h
lacl vf_spwm_varl
LDP #0E0H
SACL SCITXBUF
b start_loop1
notspwm_comp_key
ldp #04h
lacc option
sub #72h
bcnd notsvpwm_comp_key,neq
call _co
ldp #04h
lacl option
LDP #0E0H
SACL SCITXBUF
svpwm_comp_key
call _ci
lacl SCIRXBUF
and #00ffh
ldp #04h
sacl svpwm_cenvarl
call _ci
lacl SCIRXBUF
and #00ffh
ldp #04h
sacl svpwm_cenvarh
lacc svpwm_cenvarl,8
or svpwm_cenvarh
sacl min_v
b wangcheng
notsvpwm_comp_key
ldp #04h
lacc option
sub #73h ;(PC<-->04H)
bcnd notzzkz,neq
call _co
ldp #04h
lacl option
LDP #0E0H
SACL SCITXBUF
zzkz
ldp #04h
splk #01h,spwm_r_flag
splk #01h,svpwm_r_flag
b wangcheng
notzzkz
ldp #04h
lacc option
sub #74h ;(PC<-->04H)
bcnd nofzkz,neq
call _co
ldp #04h
lacl option
LDP #0E0H
SACL SCITXBUF
fzkz
ldp #04h
splk #00h,spwm_r_flag
splk #00h,svpwm_r_flag
b wangcheng
nofzkz
ldp #04h
lacc option
sub #75h ;(PC<-->04H)
bcnd notvf_spwm_highcomp,neq
call _co
ldp #04h
lacl option
LDP #0E0H
SACL SCITXBUF
vf_spwm_highcomp
ldp #04h
splk #05h,vf_spwm_num
splk #60h,vf_spwm_count
b wangcheng
notvf_spwm_highcomp
ldp #04h
lacc option
sub #76h ;(PC<-->04H)
bcnd notvf_svpwm_highcomp,neq
call _co
ldp #04h
lacl option
LDP #0E0H
SACL SCITXBUF
vf_svpwm_highcomp
ldp #04h
splk #170,vf_svpwm_cofi
splk #60h,vf_svpwm_num
notvf_svpwm_highcomp
wangcheng
b start_loop1 ;query other keys pressed
;-----------------------------------------------------------------------
serial_int:
LDP #0E1H
LACL OCRA ;configure the I/O port
AND #0FFh
SACL OCRA
SPLK #0F0H,OCRB
LACL OCRB
AND #3FH
SACL OCRB ;configure the iopc6/iopc7 general I/O
SPLK #0000H,PADATDIR ;set the PB as input
SPLK #00FFH,PBDATDIR
SPLK #0C0FFH,PCDATDIR ;configure the iopc6/iopc7 as output
* Serial communication initialization
***********************************************************
ldp #0E0H
splk #0017h,SCICCR ;one stop bit, no parity, 8bits
splk #0013h,SCICTL1 ;enable RX, TX, clk
splk #0022h,SCIPC2 ;I/O setting
splk #0000h,SCICTL2 ;disable SCI interrupts
splk #0000h,SCIHBAUD ;MSB |
splk #0081h,SCILBAUD ;LSB |19200 Baud for sysclk 10MHz
LDP #0E0H
LACL SCICTL1
OR #0020H
SACL SCICTL1
; splk #0033h,SCICTL1 ;end initialization
***********************************************************
ldp #04h ;point to variables
splk #0,add_var
splk #0,sub_var
splk #0,add_var_h
splk #0,add_var_l
splk #0,add_cen
splk #0h,add_pn
splk #01h,comm_flag
splk #0,count_h
splk #0,count_l ;initialize the display
SPLK #15,LED0
SPLK #15,LED1
SPLK #15,LED2
SPLK #01,LED3
setc intm
CALL DIS
clrc intm
RET
;----------------------------------------------------------------------------
spwm_ini_pwm
LDP #0e8h
SPLK #666H,ACTR ;
SPLK #1fE0H,DBTCON
SPLK #0207H,COMCON
SPLK #08707H,COMCON
SPLK #t1period,T1PR ;set the pwm frequency=20kHZ
SPLK #0,T2PR ;Init GP Timer 2 period that determines the sampling frequence of speed loop.
SPLK #0,T3PR
SPLK #0000H,T1CNT
SPLK #0000H,T2CNT
SPLK #0000H,T3CNT
SPLK #2802h,T1CON
SPLK #0000000000000000b,T2CON
SPLK #0000000000000000b,T3CON
SPLK #0,T1CMPR ;Let GP Timer compare outputs toggle(to have more things I can
SPLK #0,T2CMPR ;look at with an oscilloscope).
SPLK #0,T3CMPR
SPLK #t1compare,CMPR1
SPLK #t1compare,CMPR2
SPLK #t1compare,CMPR3 ;
LDP #0e8h
LACC GPTCON ; General-purpose timer control register
OR #0080H ; mask for enabling ADC start on GPT1
AND #0FFFFH ; mask for enabling ADC start on GPT1 Period Event
SACL GPTCON ; seting T1 period interrupt flag, set T1 period interrup flag
; to start A/D conversion
RET
;----------------------------------------------------------------------------
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