📄 fads.h
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/*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled */#define CFG_PISCR (PISCR_PS | PISCR_PITF)/*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 *----------------------------------------------------------------------- * Set clock output, timebase and RTC source and divider, * power management and some other internal clocks */#define SCCR_MASK SCCR_EBDF11#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)/*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22 *----------------------------------------------------------------------- * set the PLL, the low-power modes and the reset control */#ifndef CFG_PLPRCR#define CFG_PLPRCR PLPRCR_TEXPS#endif/*----------------------------------------------------------------------- * *----------------------------------------------------------------------- * */#define CFG_DER 0/* Because of the way the 860 starts up and assigns CS0 the* entire address space, we have to set the memory controller* differently. Normally, you write the option register* first, and then enable the chip select by writing the* base register. For CS0, you must write the base register* first, followed by the option register.*//* * Init Memory Controller: * * BR0/OR0 (Flash) * BR1/OR1 (BCSR) *//* the other CS:s are determined by looking at parameters in BCSRx */#define BCSR_ADDR ((uint) 0xFF080000)#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask *//* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )/* BCSRx - Board Control and Status Registers */#define CFG_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V)/* * Internal Definitions * * Boot Flags */#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */#define BOOTFLAG_WARM 0x02 /* Software reboot *//* values according to the manual */#define PCMCIA_MEM_ADDR ((uint)0xFF020000)#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))#define BCSR0 ((uint) (BCSR_ADDR + 0x00))#define BCSR1 ((uint) (BCSR_ADDR + 0x04))#define BCSR2 ((uint) (BCSR_ADDR + 0x08))#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))#define BCSR4 ((uint) (BCSR_ADDR + 0x10))/* * (F)ADS bitvalues by Helmut Buchsbaum * * See User's Manual for a proper * description of the following structures */#define BCSR0_ERB ((uint)0x80000000)#define BCSR0_IP ((uint)0x40000000)#define BCSR0_BDIS ((uint)0x10000000)#define BCSR0_BPS_MASK ((uint)0x0C000000)#define BCSR0_ISB_MASK ((uint)0x01800000)#define BCSR0_DBGC_MASK ((uint)0x00600000)#define BCSR0_DBPC_MASK ((uint)0x00180000)#define BCSR0_EBDF_MASK ((uint)0x00060000)#define BCSR1_FLASH_EN ((uint)0x80000000)#define BCSR1_DRAM_EN ((uint)0x40000000)#define BCSR1_ETHEN ((uint)0x20000000)#define BCSR1_IRDEN ((uint)0x10000000)#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)#define BCSR1_BCSR_EN ((uint)0x02000000)#define BCSR1_RS232EN_1 ((uint)0x01000000)#define BCSR1_PCCEN ((uint)0x00800000)#define BCSR1_PCCVCC0 ((uint)0x00400000)#define BCSR1_PCCVPP_MASK ((uint)0x00300000)#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)#define BCSR1_RS232EN_2 ((uint)0x00040000)#define BCSR1_SDRAM_EN ((uint)0x00020000)#define BCSR1_PCCVCC1 ((uint)0x00010000)#define BCSR1_PCCVCCON BCSR1_PCCVCC0#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)#define BCSR2_FLASH_PD_SHIFT 28#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)#define BCSR2_DRAM_PD_SHIFT 23#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)#define BCSR2_DBREVNR_MASK ((uint)0x00030000)#define BCSR3_DBID_MASK ((ushort)0x3800)#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)#define BCSR3_BREVNR0 ((ushort)0x0080)#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)#define BCSR3_BREVN1 ((ushort)0x0008)#define BCSR3_BREVN2_MASK ((ushort)0x0003)#define BCSR4_ETHLOOP ((uint)0x80000000)#define BCSR4_TFPLDL ((uint)0x40000000)#define BCSR4_TPSQEL ((uint)0x20000000)#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)#define BCSR4_FETH_EN ((uint)0x08000000)#define BCSR4_FETHCFG0 ((uint)0x04000000)#define BCSR4_FETHFDE ((uint)0x02000000)#define BCSR4_FETHCFG1 ((uint)0x00400000)#define BCSR4_FETHRST ((uint)0x00200000)#ifdef CONFIG_MPC823#define BCSR4_USB_EN ((uint)0x08000000)#endif /* CONFIG_MPC823 */#ifdef CONFIG_MPC860SAR#define BCSR4_UTOPIA_EN ((uint)0x08000000)#endif /* CONFIG_MPC860SAR */#ifdef CONFIG_MPC860T#define BCSR4_FETH_EN ((uint)0x08000000)#endif /* CONFIG_MPC860T */#ifdef CONFIG_MPC823#define BCSR4_USB_SPEED ((uint)0x04000000)#endif /* CONFIG_MPC823 */#ifdef CONFIG_MPC860T#define BCSR4_FETHCFG0 ((uint)0x04000000)#endif /* CONFIG_MPC860T */#ifdef CONFIG_MPC823#define BCSR4_VCCO ((uint)0x02000000)#endif /* CONFIG_MPC823 */#ifdef CONFIG_MPC860T#define BCSR4_FETHFDE ((uint)0x02000000)#endif /* CONFIG_MPC860T */#ifdef CONFIG_MPC823#define BCSR4_VIDEO_ON ((uint)0x00800000)#endif /* CONFIG_MPC823 */#ifdef CONFIG_MPC823#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)#endif /* CONFIG_MPC823 */#ifdef CONFIG_MPC860T#define BCSR4_FETHCFG1 ((uint)0x00400000)#endif /* CONFIG_MPC860T */#ifdef CONFIG_MPC823#define BCSR4_VIDEO_RST ((uint)0x00200000)#endif /* CONFIG_MPC823 */#ifdef CONFIG_MPC860T#define BCSR4_FETHRST ((uint)0x00200000)#endif /* CONFIG_MPC860T */#ifdef CONFIG_MPC823#define BCSR4_MODEM_EN ((uint)0x00100000)#endif /* CONFIG_MPC823 */#ifdef CONFIG_MPC823#define BCSR4_DATA_VOICE ((uint)0x00080000)#endif /* CONFIG_MPC823 */#ifdef CONFIG_MPC850#define BCSR4_DATA_VOICE ((uint)0x00080000)#endif /* CONFIG_MPC850 *//* BSCR5 exists on MPC86xADS and Duet ADS only */#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000)#define BCSR5 (CFG_PHYDEV_ADDR + 0x300)#define BCSR5_MII2_EN 0x40#define BCSR5_MII2_RST 0x20#define BCSR5_T1_RST 0x10#define BCSR5_ATM155_RST 0x08#define BCSR5_ATM25_RST 0x04#define BCSR5_MII1_EN 0x02#define BCSR5_MII1_RST 0x01/* We don't use the 8259.*/#define NR_8259_INTS 0/* Machine type*/#define _MACH_8xx (_MACH_fads)/*----------------------------------------------------------------------- * PCMCIA stuff *----------------------------------------------------------------------- */#define CFG_PCMCIA_MEM_ADDR (0xE0000000)#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )#define CFG_PCMCIA_DMA_ADDR (0xE4000000)#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )#define CFG_PCMCIA_IO_ADDR (0xEC000000)#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )/*----------------------------------------------------------------------- * IDE/ATA stuff *----------------------------------------------------------------------- */#define CONFIG_MAC_PARTITION 1#define CONFIG_DOS_PARTITION 1#define CONFIG_ISO_PARTITION 1#undef CONFIG_ATAPI#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */#undef CONFIG_IDE_LED /* LED for ide not supported */#undef CONFIG_IDE_RESET /* reset for ide not supported */#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR#define CFG_ATA_IDE0_OFFSET 0x0000/* Offset for data I/O */#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)/* Offset for normal register accesses */#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)/* Offset for alternate registers */#define CFG_ATA_ALT_OFFSET 0x0000#define CONFIG_DISK_SPINUP_TIME 1000000#undef CONFIG_DISK_SPINUP_TIME /* usin⌨️ 快捷键说明
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