📄 main.lst
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C51 COMPILER V7.00 MAIN 03/14/2005 14:49:37 PAGE 1
C51 COMPILER V7.00, COMPILATION OF MODULE MAIN
OBJECT MODULE PLACED IN MAIN.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE MAIN.C BROWSE DEBUG OBJECTEXTEND
stmt level source
1 /***************************************************************
2 程序程序：SPWM通信程序
3 功能描述：
4 该程序是基于AT89C51RD2的SPWM通信程序，用于完成精确电源控制。
5 ****************************************************************/
6
7 #include <reg51.h>
8 #include <absacc.h>
9
10 #define uchar unsigned char
11 #define uint unsigned int
12
13 //sfr WMCON = 0x96; /* Watchdog and Memory Control Register */
14 //#define WDTC() (WMCON |= 0x02)
15
16
17 #define DEF_INT_EX0 0
18 #define DEF_INT_TIME0 1
19 #define DEF_INT_EX1 2
20 #define DEF_INT_TIME1 3
21 #define DEF_INT_ASYNC 4
22 #define TIMER2_VECTOR_NUMBER 5
23
24 /***********************************
25 AD3 AD2 AD1 AD0 REGISTER
26 0 0 0 0 R0
27 0 0 0 1 R1
28 0 0 1 0 R2
29 0 0 1 1 R3
30 0 1 0 0 R4
31 0 1 0 1 R5
32 1 1 1 0 R14
33 1 1 1 1 R15
34 ************************************/
35
36 #define SPWM_R0 XBYTE[0XFFF0]
37 #define SPWM_R1 XBYTE[0XFFF1]
38 #define SPWM_R2 XBYTE[0XFFF2]
39 #define SPWM_R3 XBYTE[0XFFF3]
40 #define SPWM_R4 XBYTE[0XFFF4]
41 #define SPWM_R5 XBYTE[0XFFF5]
42 #define SPWM_R14 XBYTE[0XFFFE]
43 #define SPWM_R15 XBYTE[0XFFFF]
44
45
46 void Spwm_Init(void);
47 void Spwm_Control(void);
48
49 //-----Public Variable declare----
50 //unsigned long data SYSTIME ;
51 //unsigned long data TempCount;
52
53 /***************************
54 ***get current SYSTIME value.
55 ****************************/
C51 COMPILER V7.00 MAIN 03/14/2005 14:49:37 PAGE 2
56 //unsigned long GET_COUNT()
57 //{
58 // unsigned long tempcount;
59 // ET2 = 0;
60 // tempcount = SYSTIME;
61 // ET2 = 1;
62 // return tempcount;
63 //}
64
65 /*************************
66 Timer 2 interval 10 ms
67 **************************/
68 //void timer2() interrupt TIMER2_VECTOR_NUMBER
69 //{
70 // TF2 = 0;
71 // SYSTIME ++;
72 //}
73
74 /*************************
75 函数名称：Delay(uint x)
76 函数功能：延时 x * 10 ms,最长65535 * 10 ms
77 **************************/
78 /*void Delay(uint x)
79 {
80 unsigned long CT;
81 // CT = GET_COUNT();
82 while(GET_COUNT() - CT < x)
83 {
84 // WDTC();
85 // PCON = PCON | 0x01;
86 }
87 }*/
88 void Delay(unsigned int x)
89 {
90 1 unsigned char j;
91 1 while(x--)
92 1 {for(j=0;j<125;j++)
93 2 {;}
94 2 }
95 1 }
96 /*void _SysInit(void)
97 {
98 EA = 0;
99 IT1 = 0x01;
100 // RCAP2H = 0xDC; //11.0592M
101 // RCAP2L = 0x00;
102 RCAP2H = 0xe8; //7.3728
103 RCAP2L = 0x00;
104 TH2 = 0xDC;
105 TL2 = 0x00;
106 TR2 = 1;
107 ET2 = 1;
108 EA = 1;
109 }*/
110 /*************************
111 初始化函数：Spwm_Init()
112 **********************************************************************
113 7 6 5 4 3 2 1 0
114
115 R0 FRS2 FRS1 FRS0 X X CFS2 CFS1 CFS0
116
117 R1 X PDT6 PDT5 PDT4 PDT3 PDT2 PDT1 PDT0
C51 COMPILER V7.00 MAIN 03/14/2005 14:49:37 PAGE 3
118
119 R2 X X PDY5 PDY4 PDY3 PDY2 PDY1 PDY0
120
121 R3 X X AC O O X WS1 WS0
122
123 R4 WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8
124
125 R5 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
126
127 **************************/
128 void Spwm_Init()
129 {
130 1 SPWM_R0 =0x82;//100 010
131 1 /**********************************************************************
132 1 Carrier Frequency (CFS)
133 1 Defines the frequency of the triangular waveform to which
134 1 the power waveform is compared
135 1 The carrier frequency, fCARR, is then given by:
136 1 fCARR =
137 1 fCLK/512 x 2的（N+1）次方(n=0--7)
138 1 where fCLK = clock input frequency.
139 1 **********************************************************************
140 1 Power Frequency Range (FRS)
141 1 In order to optimise the frequency resolution of the SA4828,
142 1 the required range of power frequencies may be selected using
143 1 this parameter. Within the selected range, the frequency may
144 1 be set with 16-bit resolution.
145 1 The power frequency range, fRANGE, is then given by:
146 1 fRANGE =fCARR*2 的N 次方/384 （N=0--6）
147 1 where fCARR = carrier frequency
148 1 ***********************************************************************/
149 1 SPWM_R1 = 0x50;//1010000
150 1 /**********************************************************************
151 1 Pulse Delay Time (Underlap) (PDY)
152 1 The pulse delay time, tpdy, is then given by:
153 1 Tpty = (63-PDY)/fCARR*512 (PDY=0--63)
154 1 where fCARR = carrier frequency.
155 1 ***********************************************************************/
156 1 SPWM_R2 = 0x2f;
157 1 /**********************************************************************
158 1 Pulse Deletion Time (PDT)
159 1 To eliminate short pulses the true PWM train is passed
160 1 through a pulse deletion circuit. The pulse deletion circuit compares
161 1 pulse widths with the pulse deletion time set in the Initialisation
162 1 Register.
163 1 The pulse deletion time, tpd, is then given by:
164 1 Tpd = (127-PDT)/fCARR*512 (PDT=0--127)
165 1 where fCARR = carrier frequency.
166 1 ***********************************************************************/
167 1 SPWM_R3 = 0x01;//00000001
168 1 /**********************************************************************
169 1 WS1 WS0 Waveform
170 1 0 0 Sinusoid (default)
171 1 0 1 Triplen (harmonic injection)
172 1 1 0 Deadbanded Triplen (switching loss reduction)
173 1 1 1 Reserved
174 1 Amplitude Control (AC)
175 1 which controls
176 1 the amplitude control mode for each of the three phases.
177 1 When the AC bit is cleared the red Amplitude byte in the Control
178 1 Register is used to define the amplitude of all three phases.
179 1 When the AC bit is set, the individual Amplitude bytes, Red,
C51 COMPILER V7.00 MAIN 03/14/2005 14:49:37 PAGE 4
180 1 Yellow and Blue in the Control Register are used to define the
181 1 amplitudes of the respective phases.
182 1 ***********************************************************************/
183 1 SPWM_R4 = 0x00;
184 1 SPWM_R5 = 0x00;
185 1 /**********************************************************************
186 1 Watchdog Timer (WD)
187 1 The Watchdog Timer consists of a 16-bit programmable
188 1 counter, which is decremented at a sub-multiple of the fCLK frequency.
189 1 If the counter is allowed to reach its terminal condition(time-out),
190 1 then the PWM outputs are set to the off (low) state
191 1 and the TRIP output asserted low.
192 1 The time-out period twd, is given by the formula:
193 1 Twd=TIM*1024/fCLK (TIM=0--65535 )
194 1 **********************************************************************/
195 1 SPWM_R14 = 0x00;
196 1 }
197
198 /*************************
199 CONTROL REGISTER FUNCTIONS
200 **********************************************************************
201 7 6 5 4 3 2 1 0
202
203 R0 PFS7 PFS6 PFS5 PFS4 PFS3 PFS2 PFS1 PFS0
204
205 R1 PFS15 PFS14 PFS13 PFS12 PFS11 PFS10 PFS9 PFS8
206
207 R2 RST X X X WTE /CR /INH /F\R
208
209 R3 RAMP7 RAMP6 RAMP5 RAMP4 RAMP3 RAMP2 RAMP1 RAMP0
210
211 R4 BAMP7 BAMP6 BAMP5 BAMP4 BAMP3 BAMP2 BAMP1 BAMP0
212
213 R5 YAMP7 YAMP6 YAMP5 YAMP4 YAMP3 YAMP2 YAMP1 YAMP0
214
215 **************************/
216
217
218 void Spwm_Control()
219 {
220 1 SPWM_R0 =0x66;//01100110
221 1 SPWM_R1 =0x66;//01100110
222 1 /**********************************************************************
223 1 Power Frequency (PFS)
224 1 The power frequency ( fPOWER) is given by:
225 1 fPOWER = fRANGE*PFS/65536
226 1 COUNTER RESET BIT
227 1 where PFS = decimal value of the 16-bit PFS word and
228 1 fRANGE = power frequency range set in the Initialisation Register.
229 1 **********************************************************************/
230 1 SPWM_R2 = 0x06;//00000110
231 1 /**********************************************************************
232 1 R2 RST X X X WTE /CR /INH /F\R
233 1 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
234 1 Forward/Reverse (F/R)
235 1 The phase sequence of the three-phase PWM output waveforms
236 1 is controlled by the Forward/Reverse bit F/R.
237 1 In the forward mode the output phase sequence is red-yellow-
238 1 blue and in the reverse mode the sequence is blue-yellow_red.
239 1 Power Frequency (PFS)
240 1 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
241 1 Output Inhibit ( /INH)
C51 COMPILER V7.00 MAIN 03/14/2005 14:49:37 PAGE 5
242 1 When active (i.e., low) the output inhibit bit INH sets all the
243 1 PWM outputs to the off (low) state.
244 1 No other internal operation
245 1 of the device is affected. When the inhibit is released, the phase
246 1 bottom outputs are driven high for a whole carrier cycle before
247 1 the phase top outputs are enabled. This allows time for the capacitors
248 1 in bootstrap drive circuits to be charged.
249 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
250 1 Counter Reset (/CR)
251 1 This facility allows the internal power frequency phase counter
252 1 to be set to 0° (red phase) while Counter Reset (CR) is low.
253 1 Normal frequency control is suspended; the red phase outputs
254 1 have 50% duty cycle and yellow and blue phases have duty
255 1 cycles corresponding to +120° and -120⌨️ 快捷键说明
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