📄 chipset.cpp
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//implementation the function for chioset detection
#include <string.h>
#include <stdio.h>
#include "PCIFunc.h"
#include "Chipset.h"
#include "Tools.h"
//get the Chipset Information and fill in the structure
BOOL GetChipSetInfo(CHIPSETINFO *pChipSetInfo)
{
BOOL bRet = TRUE;
BOOL ChipsetFound;
BYTE Pos, NorthRev, SouthRev, NorthPos, SouthPos;
WORD SouthMan, SouthId, NorthMan, NorthId;
//#1 Search for the North Bridge chip
/*Just to catch the theoretical case where
the north bridge is NOT at bus 0, dev 0, func 0 - which should normally
not be the case, but you never know and it doesn't hurt as this thing
tests bus 0, dev 0, func 0 first and immediately exits if found.
*/
for ( Pos = 0; Pos !=0xFF; Pos++ )
{
//get PCI Value from 03--00(DWORD)
if (ReadPCIDword( 0x0, (long(Pos >> 3))&0x1F , Pos & 0x07, 0x00 ) != 0xFFFF )
{//we have found one PCI device
if( (ReadPCIDword( 0x0, (long(Pos >> 3))&0x1F , Pos & 0x07, 0x08 ) >> 8 ) == 0x60000 )
{//this is the north bridge Chip so break;
break;
}
}
}
if ( Pos == 0xFF ) //can't locate the North Bridge so return FALSE
{
bRet = FALSE;
return bRet;
}
NorthPos = Pos;
//Get north bridge MID & DID & rev ID
NorthMan = ReadPCIDword( 0x0, (long(NorthPos >> 3))&0x1F, NorthPos & 0x07, 0x00 );
NorthId = ReadPCIDword( 0x0, (long(NorthPos >> 3))&0x1F, NorthPos & 0x07, 0x00 ) >> 16;
NorthRev = ReadPCIDword( 0x0, (long(NorthPos >> 3))&0x1F, NorthPos & 0x07, 0x08 );
//#2 Locate south bridge
for ( Pos = 0; Pos != 0xFF; Pos++ )
{
if ( (ReadPCIDword( 0x0, (long(Pos >> 3))&0x1F, Pos & 0x07, 0x00 ) & 0xFFFF ) != 0xFFFF )
{
if( ( ReadPCIDword( 0x0, (long(Pos >> 3))&0x1F, Pos & 0x07, 0x08 ) >> 8 ) == 0x60100 )
{
break;
}
}
}
if ( Pos == 0xFF )//we can't find South Bridge so we Check if this is i430MX
{
for ( Pos = 0; Pos != 0xFF; Pos++ )
{
if ( (ReadPCIDword( 0x0, Pos >> 3, Pos & 0x07, 0x00 ) & 0xFFFF ) != 0xFFFF )
{
if( ( ReadPCIDword( 0x0, Pos >> 3, Pos & 0x07, 0x08 ) >> 8 ) == 0x68000 )
{
break;
}
}
}
}
if(Pos == 0xFF) //we can't find South Bridge so return FALSE;
{
bRet = FALSE;
return bRet;
}
SouthPos = Pos;
//Get south bridge MID & DID & rev ID
SouthMan = ReadPCIDword( 0x00, (long(SouthPos >> 3))&0x1F, SouthPos & 0x07, 0x00 );
SouthId = ReadPCIDword( 0x00, (long(SouthPos >> 3))&0x1F, SouthPos & 0x07, 0x00 ) >> 16;
SouthRev = ReadPCIDword( 0x00, (long(SouthPos >> 3))&0x1F, SouthPos & 0x07, 0x08 );
//#3 judge the North Bridge Information
BYTE SbId, NbId;
WORD NorthFunc , SouthFunc;
NorthFunc = 0x0000; /*No special treatment necessary*/
SouthFunc = 0x0000; /*No special treatment necessary*/
/*Id northbridge*/
NbId = 0; /*not recognised yet*/
switch (NorthMan)
{
case 0x8086: /*Intel*/
switch(NorthId)
{
case 0x04A3:
switch (NorthRev)
{
case 0x00:
case 0x01:
case 0x02:
case 0x03:
NbId = 0x01; /*82433LX*/
break;
case 0x10:
case 0x11:
NbId = 0x02; /*82433NX*/
break;
}
break;
case 0x122D:
NbId = 0x03;
break;/*82437FX*/
case 0x1235:
NbId = 0x04;
break; /*82437MX*/
case 0x1237:
NbId = 0x05;
break; /*82441FX*/
case 0x1250:
NbId = 0x06;
break; /*82439HX*/
case 0x7030:
NbId = 0x07;
break; /*82437VX*/
case 0x7100:
NbId = 0x08;
break; /*82439TX*/
case 0x7180:
NbId = 0x09;
break; /*82443LX/EX*/
case 0x7190:
case 0x7192:
NbId = 0x0A;
break; /*82443BX/ZX*/
case 0x71A0:
case 0x71A2:
NbId = 0x0B;
break; /*82443GX*/
case 0x84C4:
switch (NorthRev)
{
case 0x02:
NbId = 0x0C; /*82454KX*/
break;
case 0x04:
NbId = 0x0D; /*82454KX/GX, not sure*/
break;
case 0x05:
case 0x06:
NbId = 0x0E; /*82454GX*/
break;
}
break;
case 0x7120:
case 0x7122:
NbId = 0x0F; /*82810*/
break;
case 0x7124:
NbId = 0x10; /*82810E*/
break;
case 0x1130:
NbId = 0x11; /*82815*/
break;
case 0x2500:
NbId = 0x12; /*82820*/
break;
case 0x1A21:
NbId = 0x13; /*82840*/
break;
case 0x2530:
NbId = 0x14; /*82850*/
break;
case 0x2531:
NbId = 0x15; /*82860*/
break;
case 0x3575:
NbId = 0x16; /*82830MP*/
break;
case 0x1A30:
NbId = 0x17; /*82845*/
break;
}
break; //end of Intel Chip
case 0x1106: /*VIA*/
switch(NorthId)
{
case 0x0576:
NorthFunc = 0x0100; /*VIA A8/A9 scheme*/
NbId = 0x18; /*82C576M*/
break;
case 0x0585:
NbId = 0x19; /*82C585VP/VPX*/
break;
case 0x0595:
NbId = 0x1A; /*82C595*/
break;
case 0x0597:
NbId = 0x1B; /*82C597*/
break;
case 0x0598:
NbId = 0x1C; /*82C598(AT)*/
break;
case 0x0685:
NorthFunc = 0x0100; /*VIA A8/A9 scheme*/
NbId = 0x1D; /*82C685*/
break;
case 0x0501:
NbId = 0x1E; /*8501*/
break;
case 0x0691:
NbId = 0x1F; /*82C691/693(A)/694X*/
break;
case 0x0693:
NbId = 0x20; /*82C693(A)*/
break;
case 0x0601:
NbId = 0x21; /*82C601*/
break;
case 0x0605:
NbId = 0x22; /*8605*/
break;
case 0x0391:
NbId = 0x23; /*82371*/
break;
case 0x0305:
NbId = 0x24; /*8363(A)*/
break;
case 0x3099:
NbId = 0x25; /*8366*/
break;
case 0x3091:
NbId = 0x26; /*8633*/
break;
case 0x3101:
NbId = 0x27; /*8653*/
break;
case 0x3102:
NbId = 0x28; /*8662*/
break;
case 0x3103:
NbId = 0x29; /*8615*/
break;
case 0x3112:
NbId = 0x2A; /*8361*/
break;
case 0x3133:
NbId = 0x2B; /*3133*/
break;
}
break;
case 0x1022: /*AMD*/
switch(NorthId)
{
case 0x7006:
NbId = 0x30; /*AMD-751*/
break;
case 0x700E:
NbId = 0x31; /*AMD-761*/
break;
case 0x700C:
NbId = 0x32; /*AMD-762*/
break;
}
break;
case 0x1045: /*Opti*/
break;
case 0x1060: /*UMC*/
break;
case 0x1039: /*SiS*/
SouthFunc = 0x0503; /*SiS reg. 45 bits 5,2*/
switch(NorthId)
{
case 0x0496: /*85C496+497*/
NorthFunc = 0x0200; /*SiS reg. D0 scheme*/
SouthFunc = 0;
NbId = 0x33;
break;
case 0x0406: /*501/5101/5501*/
SouthFunc = 0x0501; /*SiS internal reg. 80h*/
NbId = 0x34;
break;
case 0x5511: /*5511*/
SouthFunc = 0x0502; /*SiS internal reg. 50h*/
NbId = 0x35;
break;
case 0x5571:
NbId = 0x36; /*5571*/
break;
case 0x5591:
NbId = 0x37; /*5591/5592*/
break;
case 0x5596: /*5596*/
SouthFunc = 0x0502; /*SiS internal reg. 50h*/
NbId = 0x38;
break;
case 0x5597:
NbId = 0x39; /*5597/5598/5581/5120*/
break;
case 0x0530:
NbId = 0x3A; /*530*/
break;
case 0x0540: /*540*/
SouthFunc = 0x0504; /*SiS reg. 45 bits 7,6*/
NbId = 0x3B;
break;
case 0x5600:
NbId = 0x3C; /*600*/
break;
case 0x0620:
NbId = 0x3D; /*620*/
break;
case 0x0630: /*630*/
SouthFunc = 0x0504; /*SiS reg. 45 bits 7,6*/
NbId = 0x3E;
break;
}
break;
case 0x10B9: /*ALi*/
switch(NorthId)
{
case 0x1621:
NbId = 0x2C; /*M1621*/
break;
case 0x1541:
NbId = 0x2D; /*M1541*/
break;
case 0x1641:
NbId = 0x2E; /*M1641*/
break;
case 0x1741:
NbId = 0x2F; /*M1741*/
break;
}
break;
case 0x1166: /*Reliance/ServerWorks*/
switch(NorthId)
{
case 0x0007:
NbId = 0x3F; /*NB6635*/
break;
case 0x0008:
NbId = 0x40; /*NB6536*/
break;
}
break;
case 0x1066: /*PicoPower*/
switch(NorthId)
{
case 0x0001:
NbId = 0x41; /*Vesuvius V1-LS*/
break;
}
break;
case 0x1078: /*Cyrix*/
switch(NorthId)
{
case 0x0001:
NbId = 0x42; /*Geode GX1/Cyrix MediaGX*/
break;
}
break;
default:
;
}
//#4 judge the South Bridge Information
/*Id southbridge*/
SbId = 0; /*not recognised yet*/
switch(SouthMan)
{
case 0x8086: /*Intel*/
if (Hi(SouthId) == 0x24)
SouthFunc = 0x0200;
else
SouthFunc = 0x0100;
switch(SouthId)
{
case 0x0484:
SbId = 0x02; /*82379AB SIO.A*/
break;
case 0x122E:
SbId = 0x03; /*82371FB PIIX*/
SouthFunc ++;
break;
case 0x1234:
SbId = 0x04; /*82371MX MPIIX*/
break;
case 0x7000:
SbId = 0x05 /*82371SB PIIX3*/;
SouthFunc ++;
break;
case 0x7110:
SbId = 0x06; /*82371AB PIIX4*/
SouthFunc += 3 ;
break;
case 0x2410:
SbId = 0x07; /*i82801AA ICH*/
break;
case 0x2420:
SbId = 0x08; /*i82801AB ICH0*/
break;
case 0x2440:
SbId = 0x09; /*i82801BA ICH2*/
break;
case 0x244C:
SbId = 0x0A; /*i82801BAM ICH2-M*/
break;
case 0x248C:
SbId = 0x0B; /*i82830CAM ICH3-M*/
break;
}
break;
case 0x1106: /*VIA*/
SouthFunc = 0x0300; /*VIA/AMD method*/
switch(SouthId)
{
case 0x0586:
SbId = 0x0C;
break;
case 0x0596:
SbId = 0x0D; /*VT82C596(A|B)*/
SouthFunc ++;
break;
case 0x0686:
SbId = 0x0E; /*VT82C686(A)*/
SouthFunc ++;
break;
case 0x8231:
SbId = 0x0F; /*VT8231*/
break;
case 0x3074:
SbId = 0x10; /*VT8233*/
break;
}
break;
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