📄 selectrm.cpp
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//implementation the function for chioset detection
#include <string.h>
#include <stdio.h>
#include <dos.h>
#include "PCIFunc.h"
#include "SelectRM.h"
#include "Tools.h"
//Generic Intel chipset low ROM enable & ROM write access enable
void ROMEnable(const CHIPSETINFO* const pMyChipSet , BOOL Map )
{
long Mask;
long PIIXReg, PIIXReg2, PIIXReg3;
BOOL ROMEnabled = FALSE;
if ( ROMEnabled == Map )
return;
//AMI FLASH INTERFACE STUFF
/* if ( AMIUsed )
{
//AMI ROM MAP STUFF
if ( Map )
AMIEnable;
else
AMIDisable;
}
else
*/
//Chipset northbridge stuff
switch ( Hi( pMyChipSet->NorthFunc ) )
{
case 0x01 :
//older VIA chipsets
if ( Map )
{
outportb( 0xA8 , 0x11);
PIIXReg = inport( 0xA9 );
outportb( 0xA8 , 0x11);
outportb( 0xA9 , PIIXReg | 0x40 ); //ROM Write enable
}
else
{
outportb( 0xA8 , 0x11);
outportb( 0xA9 , PIIXReg);
}
break;
case 0x02 :
//SiS 85C496+497 chipset
if ( Map )
{
Mask = 0xF8; //write enable, 384K enable
PIIXReg = ReadPCIDword( 0x00, (pMyChipSet->NorthPos >> 3)&0x1F, pMyChipSet->NorthPos & 0x7, 0xD0 );
Write2PCIDword( 0x00, (pMyChipSet->NorthPos >> 3)&0x1F, pMyChipSet->NorthPos & 0x7, 0xD0, PIIXReg | Mask );
}
else
{
Write2PCIDword( 0x00, (pMyChipSet->NorthPos >> 3)&0x1F, pMyChipSet->NorthPos & 0x7, 0xD0, PIIXReg );
}
break;
default:
;
}
//Chipset southbridge stuff
switch ( Hi( pMyChipSet->SouthFunc ) )
{
case 0x01 :
//Intel method
if ( Map )
{
Mask = 0x00440000; //write & 128k enable
if (( pMyChipSet->SouthFunc & 1 ) != 0)
Mask = Mask | 0x800000; //512k enable
if (( pMyChipSet->SouthFunc & 2 ) != 0)
Mask = Mask | 0x2000000; //1M enable
PIIXReg = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x4C );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x4C, PIIXReg | Mask );
}
else
{
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x4C, PIIXReg );
}
break;
case 0x02 :
//Intel 8xx method
if ( Map )
{
Mask = 0x10000; //FWH Write Enable
PIIXReg = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x4C );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x4C, PIIXReg | Mask );
Mask = 0xC0000000; //FWH Decode at 0xFFF00000-0xFFFFFFFF
PIIXReg2 = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0xE0 );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0xE0, PIIXReg2 | Mask );
}
else
{
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x4C, PIIXReg );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0xE0, PIIXReg2 );
}
break;
case 0x03 :
//VIA method //AMD method is the same v1.20
if ( Map )
{
Mask = 0xC0000001; //write enable, 512K enable
if ( ( pMyChipSet->SouthFunc & 1 ) != 0 )
Mask = Mask | 0x20000000; //1M enable
PIIXReg = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x40 );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x40, PIIXReg | Mask );
}
else
{
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x40, PIIXReg );
}
break;
case 0x04 :
//ALi method
if ( Map )
{
Mask = 0x47000000; //write enable, 256K enable
PIIXReg = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x44 );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x44, PIIXReg | Mask );
//M1543C rev. B1 - supports 512K ROM
Mask = 0x1000; //512K enable
PIIXReg2 = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x78 );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x78, PIIXReg2 | Mask );
//M1535 - supports 512K ROM
Mask = 0x1000000; //512K enable
PIIXReg3 = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x7C );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x7C, PIIXReg3 | Mask );
}
else
{
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x44, PIIXReg );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x78, PIIXReg2 );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x7C, PIIXReg3 );
}
break;
case 0x05 :
//SiS methods
if ( Map )
{
Mask = 0x3; //Lower & extended BIOS enable
PIIXReg = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x40 );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x40, PIIXReg | Mask );
switch ( Lo(pMyChipSet->SouthFunc) )
{
case 0x01:
//internal reg. 80h
outport( 0x22 , 0x80 );
PIIXReg2 = inport( 0x23 );
outport( 0x22 , 0x80 );
outport( 0x23 , PIIXReg2 & 0xDF | 0x4 ); //Enable Flash ROM write
outport( 0x22 , 0x80 );
//v1.23 registers can be also at 0x70
outport( 0x22 , 0x70 );
PIIXReg3 = inport( 0x23 );
outport( 0x22 , 0x70 );
outport( 0x23 , PIIXReg3 & 0xDF | 0x4 ); //Enable Flash ROM write
outport( 0x22 , 0x70 );
break;
case 0x02:
//internal reg. 50h
outport( 0x22 , 0x50 );
PIIXReg2 = inport( 0x23 );
outport( 0x22 , 0x50 );
outport( 0x23 , PIIXReg2 & 0xDF | 0x4 ); //Enable Flash ROM write
outport( 0x22 , 0x50 );
break;
case 0x03:
//PCI reg. 45h bits 5,2
PIIXReg2 = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x44 );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x44, PIIXReg2 & 0xFFFFDFFF | 0x400 );
break;
case 0x04:
//PCI reg. 45h bits 7,6
PIIXReg2 = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x44 );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x44, PIIXReg2 & 0xFFFF7FFF | 0x4000 );
break;
default:
;
}
}
else
{
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x40, PIIXReg );
switch( Lo(pMyChipSet->SouthFunc) )
{
case 0x01:
//internal reg. 80h
outport( 0x22 , 0x80 );
outport( 0x22 , 0x80 );
outport( 0x23 , PIIXReg2 );
//v1.23 registers can be also at 0x70
outport( 0x22 , 0x70 );
outport( 0x22 , 0x70 );
outport( 0x23 , PIIXReg3 );
break;
case 0x02:
//internal reg. 50h
outport( 0x22 , 0x50 );
outport( 0x22 , 0x50 );
outport( 0x23 , PIIXReg2 );
break;
case 0x03:
case 0x04:
//PCI reg. 45h
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x44, PIIXReg2 );
break;
}
}
break;
case 0x06 :
//SMSC method
if ( Map )
{
Mask = 0x02C40000; //write & 1M enable
PIIXReg = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x4C );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x4C, PIIXReg | Mask );
}
else
{
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x4C, PIIXReg );
}
break;
case 0x07 :
//Winbond method
if ( Map )
{
PIIXReg = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x4C );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x4C, PIIXReg & 0xDF00 | 0xD000 );
}
else
{
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x4C, PIIXReg );
}
break;
case 0x08 :
//ITE methods
if ( Map )
{
switch ( Lo(pMyChipSet->SouthFunc) )
{
case 0x01:
Mask = 0xFFFF7FFF; //write enable
PIIXReg = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x44 );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x44, PIIXReg & Mask );
break;
case 0x02:
PIIXReg = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x50 );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x50, PIIXReg | 0xE0000000 & 0xFEFFFFFF );
break;
}
}
else
{
switch ( Lo(pMyChipSet->SouthFunc) )
{
case 0x01:
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x44, PIIXReg );
break;
case 0x02:
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x50, PIIXReg );
break;
}
}
break;
case 0x09 :
//Reliance method
if ( Map )
{
Mask = 0x00000200; //512K enable
PIIXReg = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x40 );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x40, PIIXReg | Mask );
Mask = 0x00000080; //4MB enable
PIIXReg2 = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x70 );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x70, PIIXReg2 | Mask );
outport( 0xC6F, inport(0xC6F) | 0x40 ); //Flash write enable
}
else
{
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x40, PIIXReg );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x70, PIIXReg2 );
outport( 0xC6F, inport(0xC6F) & 0xBF ); //Flash write disable
}
break;
case 0x10 :
//PicoPower method
if ( Map )
{
outport( 0x24 , 0x03 );
PIIXReg = inport(0x26);
outport( 0x24 , 0x03 );
outport( 0x26 , PIIXReg | 0x40 ); //Flash enable
outport( 0x24 , 0x03 );
}
else
{
outport( 0x24 , 0x03 );
outport( 0x24 , 0x03 );
outport( 0x26 , PIIXReg );
}
break;
case 0x11 :
//Cyrix method
if ( Map )
{
Mask = 0x00060000; //16MB enable, write enable
PIIXReg = ReadPCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x50 );
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x50, PIIXReg | Mask );
}
else
{
Write2PCIDword( 0x00, (pMyChipSet->SouthPos >> 3)&0x1F, pMyChipSet->SouthPos & 0x7, 0x50, PIIXReg );
}
break;
default:
;
}
ROMEnabled = Map;
}
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