📄 tyspci.c
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int busNo, deviceNo,vendor,funcNo;
int cont=TRUE;
short status;
int pBusNo,pDeviceNo,pFuncNo,i;
if (pciConfigLibInit (0, (ULONG)tysPciConfigRead,
(ULONG) tysPciConfigWrite,(ULONG) tysPciSpecialCycle) != OK)
{
printf("pciConfigLibInit error!\n");
}
if ((pciIntLibInit ()) != OK)
{
printf("pciIntLibInit error!\n");
}
/*** mot82xxBridgeInit();******************************/
*M8260_SIUMCR(INTERNAL_MEM_MAP_ADDR) = (UINT32)SIUMCR_PCI_SETTING;
* M8260_PPC_ALRH (INTERNAL_MEM_MAP_ADDR) = 0x61207893; /* Park bus on core while modifying PCI Bus accesses */
* M8260_PPC_ACR (INTERNAL_MEM_MAP_ADDR) = PPC_ACR_BUS_PARK_CORE ;
* (VUINT32*) M8260_OR8(INTERNAL_MEM_MAP_ADDR) = PCI_INT_MEM_OR8_SETTING;
* (VUINT32*) M8260_BR8(INTERNAL_MEM_MAP_ADDR) = PCI_INT_MEM_BR8_SETTING;
* (VUINT32*) PCIMSK_REG0 (INTERNAL_MEM_MAP_ADDR) = PCIMSK0_SETTING;
* (VUINT32*) PCIMSK_REG1 (INTERNAL_MEM_MAP_ADDR) = PCIMSK1_SETTING;
* (VUINT32*) PCIBR_REG0 (INTERNAL_MEM_MAP_ADDR) = PCIBR0_SETTING;
* (VUINT32*) PCIBR_REG1 (INTERNAL_MEM_MAP_ADDR) = PCIBR1_SETTING;
/* sysPciOutLong((UINT32*)(immrVal| PCI_GCR_REG) , 0); */
sysPciOutLong((UINT32*)(immrVal| PCI_GCR_REG) , EXTERNAL_PCI_BUS_ENABLE);
sysPciOutLong((UINT32*)(immrVal| PCI_INBOUND_TRANS_ADRS_REG0), 0x0000000);
sysPciOutLong((UINT32*)(immrVal| PCI_INBOUND_BASE_ADRS_REG0), PCI_MSTR_MEM_BUS>>12 & 0xfffff);
sysPciOutLong((UINT32*)(immrVal |PCI_INBOUND_COMP_MASK_REG0),
0xff000 | PCI_WINDOW_ENABLE_BIT | PCI_SNOOP_ENABLE | PCI_PREFETCHABLE);
sysPciOutLong((UINT32*)(immrVal |PCI_ERROR_MASK_REG), 0);
sysPciOutLong((UINT32*)(immrVal |PCI_PTCR_REG), 0x80FF0000);
* M8260_PPC_ALRH (INTERNAL_MEM_MAP_ADDR) = 0x30126745;
* M8260_PPC_ACR (INTERNAL_MEM_MAP_ADDR) = PPC_ACR_BUS_PARK_PCI;
result = tysPciConfigWrite(0,0,0,
PIMMR_BASE_ADRS_REGISTER_OFFSET,
PIMMR_BASE_ADRS_REGISTER_WIDTH,
PCI_BRIDGE_PIMMR_BASE_ADRS);
result = tysPciConfigWrite(0,0,0,
CLASS_OFFSET,
CLASS_WIDTH,
BRIDGE_CLASS_TYPE);
result = tysPciConfigWrite(0,0,0,
COMMAND_REGISTER_OFFSET,
COMMAND_REGISTER_WIDTH,
(PCI_SERR_ENABLE_BIT|PCI_PARITY_ERR_ENABLE_BIT|BUS_MASTER_ENABLE_BIT|MEMORY_SPACE_ACCESS_ENABLE_BIT));
/*as a bridge*/
/* 0xC: pci bus cache line size register */
result = tysPciConfigWrite(0,0,0,
CACHE_LINE_SIZE_OFFSET,
CACHE_LINE_SIZE_WIDTH,
8);
/* 0xD: pci bus latency timer register */
result = tysPciConfigWrite(0,0,0,
LATENCY_TIMER_OFFSET,
LATENCY_TIMER_WIDTH,
0x20);
status=0;
result = tysPciConfigRead(0,0,0,
LATENCY_TIMER_OFFSET,
LATENCY_TIMER_WIDTH,
&status);
printf("LATENCY_TIMER_OFFSET is 0x%x\n",status);
/* 0x46: pci bus arbiter configuration register */
result = tysPciConfigWrite(0,0,0,
ARBITER_CFG_OFFSET,
ARBITER_CFG_WIDTH,
0x80);
status=0;
result = tysPciConfigRead(0,0,0,
ARBITER_CFG_OFFSET,
ARBITER_CFG_WIDTH,
&status);
printf("ARBITER_CFG_OFFSET is 0x%x\n",status);
result = tysPciConfigWrite(0,0,0,
CFG_LOCK_OFFSET,
CFG_LOCK_WIDTH,
0x0);
status=0;
result = tysPciConfigRead(0,0,0,
CFG_LOCK_OFFSET,
CFG_LOCK_WIDTH,
&status);
printf("CFG_LOCK_OFFSET is 0x%x\n",status);
/**************sysPciAutoConfig();******************************/
/*
readresult=0;
readresult=sysPciInLong( (UINT32 *)( immrVal|0x10884) );
printf("readresult4 = 0x%x\n",readresult);
*/
/*
tysconfig();
*/
/*
for (busNo = 0; cont == TRUE && busNo <= 0; busNo++)
for (deviceNo = 0; ((cont == TRUE) && (deviceNo < 32)); ++deviceNo)
for (funcNo = 0; cont == TRUE && funcNo < 1; funcNo++)
{
vendor=0;
pciConfigInLong (busNo, deviceNo, funcNo, PCI_CFG_VENDOR_ID, &vendor);
printf("\n BUS = 0x%x DEV = 0x%x , Vendor = 0x%x" , busNo , deviceNo , vendor ) ;
readresult=0;
readresult=sysPciInLong( (UINT32 *)( immrVal|0x10884) );
printf(" readresult4 = 0x%x\n",readresult);
sysPciOutLong( (UINT32 *)( immrVal|0x10884) , readresult );
}
*/
/****************************read the pci1410a*********************/
temp16=0;
result = tysPciConfigRead(0,0x12,0,
Vendor_ID,
2,
&temp16);
printf("Vendor_ID is 0x%x\n",temp16);
temp16=0;
result = tysPciConfigRead(0,0x12,0,
Device_ID,
2,
&temp16);
printf("Device_ID is 0x%x\n",temp16);
temp16=0;
result = tysPciConfigRead(0,0x12,0,
Command,
2,
&temp16);
printf("Command is 0x%x\n",temp16);
temp16=0;
result = tysPciConfigRead(0,0x12,0,
Status,
2,
&temp16);
printf("Status is 0x%x\n",temp16);
temp8=0;
result = tysPciConfigRead(0,0x12,0,
Revision_ID,
1,
&temp8);
printf("Revision_ID is 0x%x\n",temp8);
temp32=0;
result = tysPciConfigRead(0,0x12,0,
PCI_class_code,
4,
&temp32);
printf("PCI_class_code is 0x%x\n",temp32);
temp8=0;
result = tysPciConfigRead(0,0x12,0,
Cache_line_size,
1,
&temp8);
printf("Cache_line_size is 0x%x\n",temp8);
temp8=0;
result = tysPciConfigRead(0,0x12,0,
Latency_timer,
1,
&temp8);
printf("Latency_timer is 0x%x\n",temp8);
temp8=0;
result = tysPciConfigRead(0,0x12,0,
Header_type,
1,
&temp8);
printf("Header_type is 0x%x\n",temp8);
temp8=0;
result = tysPciConfigRead(0,0x12,0,
BITS,
1,
&temp8);
printf("BITS is 0x%x\n",temp8);
temp32=0;
result = tysPciConfigRead(0,0x12,0,
CardBus_socket,
4,
&temp32);
printf("CardBus_socket is 0x%x\n",temp32);
temp8=0;
result = tysPciConfigRead(0,0x12,0,
Capability_pointer,
1,
&temp8);
printf("Capability_pointer is 0x%x\n",temp8);
temp16=0;
result = tysPciConfigRead(0,0x12,0,
Secondary_status,
2,
&temp16);
printf("Secondary_status is 0x%x\n",temp16);
temp8=0;
result = tysPciConfigRead(0,0x12,0,
PCI_bus_number,
1,
&temp8);
printf("PCI_bus_number is 0x%x\n",temp8);
temp8=0;
result = tysPciConfigRead(0,0x12,0,
CardBus_bus_number,
1,
&temp8);
printf("CardBus_bus_number is 0x%x\n",temp8);
temp8=0;
result = tysPciConfigRead(0,0x12,0,
Subordinate_bus_number,
1,
&temp8);
printf("Subordinate_bus_number is 0x%x\n",temp8);
temp8=0;
result = tysPciConfigRead(0,0x12,0,
CardBus_latency_timer,
1,
&temp8);
printf("CardBus_latency_timer is 0x%x\n",temp8);
temp32=0;
result= tysPciConfigWrite(0,0x12,0,Memory_base_0,
4,
0xffffffff);
result = tysPciConfigRead(0,0x12,0,
Memory_base_0,
4,
&temp32);
printf("Memory_base_0 is 0x%x\n",temp32);
temp32=0;
result= tysPciConfigWrite(0,0x12,0,Memory_limit_0,
4,
0xffffffff);
result = tysPciConfigRead(0,0x12,0,
Memory_limit_0,
4,
&temp32);
printf("Memory_limit_0 is 0x%x\n",temp32);
temp32=0;
result= tysPciConfigWrite(0,0x12,0,Memory_base_1,
4,
0xffffffff);
result = tysPciConfigRead(0,0x12,0,
Memory_base_1,
4,
&temp32);
printf("Memory_base_1 is 0x%x\n",temp32);
temp32=0;
result= tysPciConfigWrite(0,0x12,0,Memory_base_1,
4,
0xffffffff);
result = tysPciConfigRead(0,0x12,0,
Memory_limit_1,
4,
&temp32);
printf("Memory_limit_1 is 0x%x\n",temp32);
temp32=0;
result= tysPciConfigWrite(0,0x12,0,IO_base_1,
4,
0xffffffff);
result = tysPciConfigRead(0,0x12,0,
IO_base_0,
4,
&temp32);
printf("IO_base_0 is 0x%x\n",temp32);
temp32=0;
result= tysPciConfigWrite(0,0x12,0,IO_limit_1,
4,
0xffffffff);
result = tysPciConfigRead(0,0x12,0,
IO_limit_0,
4,
&temp32);
printf("IO_limit_0 is 0x%x\n",temp32);
temp32=0;
result= tysPciConfigWrite(0,0x12,0,IO_base_1,
4,
0xffffffff);
result = tysPciConfigRead(0,0x12,0,
IO_base_1,
4,
&temp32);
printf("IO_base_1 is 0x%x\n",temp32);
temp32=0;
result= tysPciConfigWrite(0,0x12,0,IO_limit_1,
4,
0xffffffff);
result = tysPciConfigRead(0,0x12,0,
IO_limit_1,
4,
&temp32);
printf("IO_limit_1 is 0x%x\n",temp32);
temp8=0;
result = tysPciConfigRead(0,0x12,0,
interrupt_line,
1,
&temp8);
printf("interrupt_line is 0x%x\n",temp8);
temp8=0;
result = tysPciConfigRead(0,0x12,0,
interrupt_pin,
1,
&temp8);
printf("interrupt_pin is 0x%x\n",temp8);
temp16=0;
result = tysPciConfigRead(0,0x12,0,
Bridge_control,
2,
&temp16);
printf("Bridge_control is 0x%x\n",tem
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