v6armiss.dsc

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;; ARMulator configuration file type 3
;; Copyright (c) 2001-2003 ARM Limited. All Rights Reserved.

;; RCS $Revision: 1.4.6.3.18.10 $
;; Checkin $Date: 2004/12/01 16:57:22 $
;; Revising $Author: ljameson $
 
;;
;; This is a non-user-edittable configuration file for ARMulator/
;; ARM Instruction Set Simulator.
;;


; Currently to allow versioning based on ordering in ARMDLL path we have
; to support multiple DLLs with the same name on the path.
; Note that at the moment the v6 model uses Flatmem from RVISS which doesn't
; check this so it always allows multiple.
ALLOW_MULTIPLE_DLLS_ON_PATH=1


;History
; D/E 185610 - "base" names changed to ARM1136J-S and  ARM1136JF-S
;       which are the CPU names used by the compiler, Multi-ICE etc.


{ PeripheralSets

;{ Processors_Common_ARMULATE=Processors_Common_No_Peripherals
;
;; The BUS model.
;{ Flatmem=Flatmem
;{Peripherals=Common_Peripherals
;}
;}
;End Processors_Common_ARMULATE


; Almost the same as Processors_Common_ARMULATE,
; but we don't want to depend on armulate.dsc.
; Differences...
; (1) Vic_PL192 instead of INTC.
{ Processors_Common_V6=Processors_Common_No_Peripherals

; Validation coprocessor config.
CP5_LDCL_WORDS=4

;This configuration-form is temporary until we have proper links.
CP15VALFIQ_NUM=1
CP15VALIRQ_NUM=11
;+++ READ AND USE!
PMUIRQ_NUM=13
; In the smvinit file, the interrupt bits 0x3f3f are enabled for normal operation with VIC. 
; The pin comnnections are as follows
   ; VICINTSOURCE[0] = ~nFIQ;           // FIQExternal                 [1]
   ; VICINTSOURCE[1] = ~nVALFIQ;        // FIQ from Sysmetrics block
   ; VICINTSOURCE[2] = 1'b0;            // can be s/w generated  
   ; VICINTSOURCE[3] = 1'b0;            // can be s/w generated
   ;     //IRQS
   ; VICINTSOURCE[4] = 1'b0;            // can be s/w generated
   ; VICINTSOURCE[5] = 1'b0;            // can be s/w generated
   ; VICINTSOURCE[6] = COMMRX;          // PL192 convention            [1]
   ; VICINTSOURCE[7] = COMMTX;          // PL192 convention
   ; VICINTSOURCE[8] = 1'b0;            // can be s/w generated (T1)
   ; VICINTSOURCE[9] = 1'b0;            // can be s/w generated (T2)
   ; VICINTSOURCE[10] = ~nIRQ;          // IRQ External                [1]
   ; VICINTSOURCE[11] = ~nVALIRQ;       // IRQ from Sysmetrics block   [1]
   ; VICINTSOURCE[12] = ~nDMAIRQ;                                  [1]
   ; VICINTSOURCE[13] = ~nPMUIRQ;                                  ???
   ; VICINTSOURCE[31:14] = 18'b0;
;[1] - NOT IMPLEMENTED YET.

;These are links created by the core.
{ LINKS
  VICVECTADDR_IN=VIC.VICVECTADDR_OUT
  ; - this link-formation is not implemented yet -
#if NotYet
  PMUIRQ_OUT=VIC.INTSOURCE[13]
  PMUFIQ_OUT=VIC.INTSOURCE[1]
#endif
}

; The BUS model.
{ Flatmem=Flatmem
      {Peripherals=Common_Peripherals

        { Intctrl=No_Intctrl
        ; The timer may not work properly if the interrupt controller is 
        ; not present
        }

        { Timer=No_Timer
        }

        { VIC=Vic_PL192
          ;VIC_BASE from validation/ include/jaguar/src/Vic_Macros
          ; and jaguar/src/jaguar-smvinit.s
          ; and src/Configuration
          ; and generic/src/Configuration-Generic.hs
          RANGE:BASE=0x3f100000
          VIC_INTSELECT=2
          VIC_INTENABLE=0x2802
          ; DEBUG_LEVEL=31
        }
      }
}

;End Processors_Common_V6
}

  { Vic_PL192
    model_dll_filename=Vic_pl192
    META_GUI_INTERFACE=Vic
  }

; End PeripheralSets
}



{ Processors



{ ARM1136J-S=Processors_Common_V6
Architecture=6
ARMJAVAV1EXTENSIONS=True
meta_moduleserver_processor=ARMV6
MODEL_DLL_FILENAME=v6armiss
; Select a (module) RDI_ProcVec
ARMulator=ARMV6
; V6 debug CP14.
DEBUG_CP14=2
; LSU fetches >all< regs before writeback!
EARLY_STM_WRITEBACK=16

;NB Only 64 and 32 are legal so far.
LSU_Width=64
PFU_Width=64
;This is for the AHB.
BUS_Width=64

CP15_IDREGVALUE=0x4107B361
TLB_IS_UNIFIED=True
; The sum of the following 2 must not exceed 1<<9 for this model.
DTLB_NONLOCKABLE_SIZE=64
DTLB_LOCKABLE_SIZE=8

;ARMV6 spec. allows this, ARM1136 doesn't.
; One way to enable write allocation is to set 
; L1_ALLOW_WRITE_ALLOCATE=True here and
;  Use V6TEX=4, C=0,B=1 in Region[1] of Pagetab.
L1_ALLOW_WRITE_ALLOCATE=False

; This should be FALSE for all known cores.
;  It is only used to answer "What If?" questions.
;L1_FORCE_WRITE_ALLOCATE=True

;Default for ARMv6 is 4,4.
ICACHE_ASSOCIATIVITY=4
DCACHE_ASSOCIATIVITY=4


;
; The cache is not modelled accurately enough to show aliasing effects for 
; cache sizes of 32K or larger
; 

; - 32k -
;ICACHE_LINES=1024
;DCACHE_LINES=1024

; L means main memory is fixed LittleEnd (R+W)
ENDIANNESS=C

; Configure Debug
Breakpoints=6
Contextpoints=2
Watchpoints=2

{RDIMSVR=RDIMSVR
target_controller_type=armulate
}

;Allow Pagetab to work.
HASMMU=True
HAS_BE8=True
HAS_ABIT=1

; LSU special-case word-swaps CP11.
VFP_ENDIANNESS_DONE_BY_CORE=True

; Specify 1 DTCRams and 1 ITCRams, 32k each
; (validation requires exactly one of each)
DTCRAM0SIZE=32768
DTCRAM1SIZE=0
DTCRAM2SIZE=0
DTCRAM3SIZE=0
ITCRAM0SIZE=32768
ITCRAM1SIZE=0
ITCRAM2SIZE=0
ITCRAM3SIZE=0

; { Trickbox configuration

;We must strip off 0x01000000 for PA-aliasing for v6mem tests.
;Tbox_MemAddrMask=0x00FFFFFF
;Tbox_MemAddrMask=0xFEFFFFFF
; - the above not quite good enough, replace by ...
DOUBLEMAPPEDBASE1=0x100000
DOUBLEMAPPEDBASE2=0x1100000
DOUBLEMAPPEDSIZE=0xA00000

;Required to pass j_wconst.
PERFORM_ABORTING_WRITES=False
; }


}


{ ARM1136JF-S=ARM1136J-S
;Support VFP
 {VFP=VFP11
 }
}


;Removed in favour of ARM1136JF-S for compatability with compiler +MultiIce.
;{ARM1136JFS=ARM1136
;}

}

; UNIREGSNAMES
; 
; This maps the processor name that we are given into a uniregs name
; that describes what coprocessors, etc. that we have.  The
; 'PROCESSOR' name is the key, the value is the Uniregs name we have
; to deliver to get the right registers.
;
; The tag is the model name (processor) and the right hand side is the
; TABS name of RVD and any extra options.

{ UNIREGSNAMES
  ARM1136JF-S = ARM1136JF-S,VFPv2
  ARM1136J-S  = ARM1136J-S
}

;; EOF v6armiss.dsc