armulate.dsc

realview22.rar

;; ARMulator configuration file type 3
;; - armulate.dsc -
;; Copyright (c) 1996-2001 ARM Limited. All Rights Reserved.

;; RCS $Revision: 1.65.2.49.2.10 $
;; Checkin $Date: 2004/11/09 17:01:25 $
;; Revising $Author: ljameson $
 
;;
;; This is the configuration file for ARMulator 
;;
ARMULATE_VERSION=120

;; Comment this out for benchmarking
; For the moment we assume that if no clock speed has been set on the
; command-line, the user wishes to use a wall-clock for timing
#if !CPUSPEED
Clock=Real
#endif


;; This line controls whether (some) models give more useful descriptions
;; of what they are on startup, and during running.
;Verbose=False

;; To enable faster watchpoints, set "WatchpointsEnabled"
WatchpointsEnabled=False

;; ARM966E-S HiVector boot control
;; Uncomment next line if you wish to boot ARM966E-S with hivecs
;ARM966BootHiVectors


;; *****************************************************************
;; ARMulator Peripheral Models
;; Central list of peripherals 
;; Use this list to enable/disable peripherals
;; *****************************************************************
;; To enable a peripheral change the rhs to TRUE
;; To disable a peripheral change the rhs to FALSE

;This is False by default.
WDogEnabled=False

; Note that DCC is enabled by default if running on a processor
; with an EmbeddedICE macrocell

;; end of peripheral list
;; *****************************************************************


;; ARMulator can tell you how much stack your program uses (at a
;; substantial runtime cost)
TrackStack=False



{ PeripheralSets

{ Processors_Common_ARMULATE=Processors_Common_No_Peripherals

;; This probably has to be loaded after after Flatmem (for now),
;; so we load it in Default_Common_Peipherals.
; Load code-sequences.
;{ Codeseq=Codeseq
;}

; The BUS model.
{ Flatmem=Flatmem
{Peripherals=Common_Peripherals
}
}

;End Processors_Common_ARMULATE
}

;End PeripheralSets
}


;;
;; This is the list of all processors supported by ARMulator.
;;

{ Processors

;; This isn't a processor.
Default=ARM7TDMI

;; Entries are of the form:
;
; { <processor-name>=<processor-prototype>
; ... features ...
; }
;


;; The "BASIC" RDI model provides models of the ARM2/ARM6/ARM7 and ARM8
;; families.
;;#if RDI_BASIC

;; ARM6 family

{ ARM6=Processors_Common_ARMULATE
CoprocessorInterfaceType=7
MODEL_DLL_FILENAME=armulate
;; Features:
Core=ARM6
ARMulator=BASIC
Architecture=3
{DCC=Default_DebugComms
}

}

;; Variants:
{ARM60=ARM6
}

;; Cached variants
;;  MEMORY_MMUlator -- must be defined.


{ARM600=ARM6
Memory=ARM600
CacheWords=4
CacheAssociativity=64
CacheBlocks=4
HASMMU=True
}

{ARM610=ARM6
Memory=ARM610
CacheWords=4
CacheAssociativity=64
CacheBlocks=4
HASMMU=True
}

;; ARM7 family

{ ARM7=Processors_Common_ARMULATE
CoprocessorInterfaceType=7
MODEL_DLL_FILENAME=armulate
;; Features:
Core=ARM7
ARMulator=BASIC
Architecture=3
Nexec
LateAborts
SubPage
{DCC=Default_DebugComms
}
AllowFPE=True
}

;; Variants of ARM7:
{ARM70=ARM7
}

;; Cached variants
{ARM700=ARM7
Memory=ARM700
CacheWords=8
CacheAssociativity=4
CacheBlocks=64
;; MMU/PU properties - used by pagetable to determine how to start
HASMMU=True
}

{ARM704=ARM7
HASMMU=True
Memory=ARM704
CacheWords=4
CacheAssociativity=4
CacheBlocks=64
}

{ARM710=ARM7
HASMMU=True
CacheWords=4
CacheAssociativity=4
CacheBlocks=128
Memory=ARM710a
}

{ARM710a=ARM7
HASMMU=True
Memory=ARM710
CacheWords=4
CacheAssociativity=4
CacheBlocks=128
}


;; ARM7D family - ARM7D and ARM70D

{ ARM7D=Processors_Common_ARMULATE
CoprocessorInterfaceType=7
MODEL_DLL_FILENAME=armulate
;; Features
Core=ARM7
ARMulator=BASIC
Architecture=3
Nexec=True
LateAborts=True
Debug=True
AllowFPE=True
{DCC=Default_DebugComms
}

}
;;Variants of ARM7D
{ARM70D=ARM7D
Debug=True
{DCC=Default_DebugComms
}
}

;; ARM7DM families
{ARM7DM=ARM7D
Architecture=3M
}

{ARM70DM=ARM7D
Architecture=3M
}



;; Thumb family

{ ARM7TDM=Processors_Common_ARMULATE
CoprocessorInterfaceType=7
MODEL_DLL_FILENAME=armulate
;; Features
meta_moduleserver_processor=ARM7TDMI
Core=ARM7
ARMulator=BASIC
Architecture=4T
Nexec=True
LateAborts=True
Debug=True
AllowFPE=True
{DCC=Default_DebugComms
}

}
;; Variants of ARM7TDM
{ARM7TDMI=ARM7TDM
}

{ARM7TM=ARM7TDM
}

;; Cached variants

{ARM720T=ARM7TDM
meta_moduleserver_processor=ARM720T
Memory=ARM720T
HighExceptionVectors=True
CacheWords=4
CacheAssociativity=4
CacheBlocks=128
HASMMU=True
}

{ARM720T-REV4=ARM7TDM
meta_moduleserver_processor=ARM720T
Memory=MMU720
HighExceptionVectors=True
CacheWords=8
CacheAssociativity=4
CacheBlocks=64
HASMMU=True
;Preferred validation environment...
TBOX=ARM720T_REV4_Trickbox
}




{ARM710T=ARM7TDM
meta_moduleserver_processor=ARM710T
Memory=ARM710T
CacheWords=4
CacheAssociativity=4
CacheBlocks=128
HASMMU=True
}

{ARM740T=ARM7TDM
{meta_moduleserver_processor=ARM740T
revision=0
}
CacheWords=4
CacheAssociativity=4
CacheBlocks=128
Memory=ARM740T
HASPU=True
;TBox_MemMask=TRUE -- obsolete, replaced by more flexible:
TBox_MemAddrMask=0x7FFFffff
}

;; Synthesisable ARM family

{ ARM7TM-S=Processors_Common_ARMULATE
CoprocessorInterfaceType=7
MODEL_DLL_FILENAME=armulate
;; Features
Core=ARM7
ARMulator=BASIC
Architecture=4T
Nexec=True
LateAborts=True
Debug=True
AllowFPE=True
{DCC=Default_DebugComms
}
}

;;Variants of ARM7TM-S

{ARM7T-S=ARM7TM-S
Architecture=4TxM
EarlySignedMultiply=True
}

{ARM7TDI-S=ARM7TM-S
Architecture=4TxM
EarlySignedMultiply=True
}

{ARM7TDMI-S=ARM7TM-S
}

;; ARM8 family

{ ARM8=Processors_Common_ARMULATE
CoprocessorInterfaceType=7
MODEL_DLL_FILENAME=armulate
;; Features:
Core=ARM8
ARMulator=BASIC
Architecture=4
Nexec=True
MultipleEarlyAborts=True
AbortsStopMultiple=True
Prefetch=True
HasBranchPrediction=True
NoLDCSTC=True
{DCC=Default_DebugComms
}
}

;; Variants of ARM8:
{ARM810=ARM8
Memory=ARM810
CacheWords=4
CacheAssociativity=64
CacheBlocks=8
HASMMU=True
}

;; Endif RDI_BASIC.
;;#endif



;; StrongARM1 family

{ StrongARM1=Processors_Common_ARMULATE
CoprocessorInterfaceType=7
MODEL_DLL_FILENAME=armulate
;; Features:
Core=StrongARM
ARMulator=STRONG
Architecture=4
Nexec=True
MultipleEarlyAborts=True
AbortsStopMultiple=True
StrongARMAware=True
NoLDCSTC=True
NoCDP=True
DEFAULT_CPUSPEED=20.24MHz
{DCC=Default_DebugComms
}
}
;;;#if MEMORY_StrongMMU
;; Variants of StrongARM:
{SA-110=StrongARM1
Memory=SA-110
ICYCLES=TRUE
HASMMU=True
}
;;;;#endif



;; ARM9 family
;

;; ARM 9E-S variants
{ ARM9E-S-REV1=Processors_Common_ARMULATE
CoprocessorInterfaceType=9
MODEL_DLL_FILENAME=armulate
;; Features:
{meta_moduleserver_processor=ARM9E-S
revision=1
}
Core=ARM9
ARMulator=ARM9ulator
Architecture=4T
Nexec=True
MultipleEarlyAborts=True
AbortsStopMultiple=True
CoreCycles=True
HighExceptionVectors=True
ARM9Extensions=True
ARM9CoprocessorInterface=True
ARMV5PEXTENSIONS=True
;;StrongARMAware
;;NoLDCSTC
;;NoCDP
{DCC=Default_DebugComms
}
}

{ ARM9E-S-REV0=Processors_Common_ARMULATE
CoprocessorInterfaceType=9
MODEL_DLL_FILENAME=armulate
;; Features:
{meta_moduleserver_processor=ARM9E-S
revision=0
}
Core=ARM9
ARMulator=ARM9ulator
Architecture=4T
Nexec=True
MultipleEarlyAborts=True
AbortsStopMultiple=True
CoreCycles=True
HighExceptionVectors=True
ARM9Extensions=True
ARM9CoprocessorInterface=True
;;StrongARMAware
;;NoLDCSTC
;;NoCDP
{DCC=Default_DebugComms
}
}



{ ARM9E-S-REV2=Processors_Common_ARMULATE
CoprocessorInterfaceType=9
{meta_moduleserver_processor=ARM9E-S
revision=2
}
Core=ARM9
ARMulator=ARM9ulator
Architecture=5T
Nexec=True
MultipleEarlyAborts=True
AbortsStopMultiple=True
CoreCycles=True
HighExceptionVectors=True
ARM9Extensions=True
ARMv5PExtensions=True
ARM9OptimizedMemory=True
ARM9OptimizedDAborts=True

ARMJavaExtensions=False
ARMJavaV1Extensions=False

ARM9CoprocessorInterface=True
{DCC=Default_DebugComms
}
}




{ ARM9EJ-S-REV1=ARM9E-S-REV2
{meta_moduleserver_processor=ARM9EJ-S
revision=1
}
;Core=ARM9
;ARMulator=ARM9ulator
;Architecture=5T
;Nexec=True
;MultipleEarlyAborts=True
;AbortsStopMultiple=True
;CoreCycles=True
;HighExceptionVectors=True
;ARM9Extensions=True
;ARMv5PExtensions=True
;ARM9OptimizedMemory=True
ARMJavaExtensions=True
ARMJavaV1Extensions=True
;ARM9CoprocessorInterface=True
;{DCC=Default_DebugComms
;}
}

{ ARM7ej-s=ARM9ej-s
VNInterface=TRUE
Memory=ARM7ej
}

{ ARM966E-S-REV0=Processors_Common_ARMULATE
CoprocessorInterfaceType=9
MODEL_DLL_FILENAME=armulate
{meta_moduleserver_processor=ARM966E-S
revision=0
}
Core=ARM9
ARMulator=ARM9ulator

;(Rev 0 is really. 5TExP, i.e. not a full 5T.)
Architecture=5T
Nexec=True
MultipleEarlyAborts=True
AbortsStopMultiple=True
CoreCycles=True
HighExceptionVectors=True
ARM9Extensions=True
;966 has neither PU nor MMU.
HASTCRAM=TRUE
HasSRAM=True
;
CHIPID=0x41049660
Memory=ARM966E_S
revision=0
; If you put either of these to zero then it will be intepreted as
; 32 KB.  Zero IRam or DRam sizes are not useful configurations!
IRamSize=0x10000
DRamSize=0x10000
ARM9CoprocessorInterface=True
{DCC=Default_DebugComms
}
}

;;(Rev 1 s.b. 5TE)
{ ARM966E-S-REV1=ARM966E-S-REV0
;; We'd like to be 5T.
Architecture=5T
ARM9CoprocessorInterface=True
ARMV5PEXTENSIONS=True
{meta_moduleserver_processor=ARM966E-S
revision=1
}
; Note that rev1 is an >architecture< upgrade, but still revision 0
; (and variant 0) in the CP15 ID register. 
CHIPID=0x41059660
HASTCRAM=TRUE
HasSRAM=True
Memory=ARM966E_S
revision=1
; If you put either of these to zero then it will be intepreted as
; 32 KB.  Zero IRam or DRam sizes are not useful configurations!
IRamSize=0x10000
DRamSize=0x10000
}


{ ARM966E-S-REV2=ARM966E-S-REV1
; We cannot yet model external TCRAM, or their timings,
; but we can model the internal 9-REV2 core.
{meta_moduleserver_processor=ARM966E-S
revision=2
}
Core=ARM9
ARMulator=ARM9ulator
Architecture=5T
Nexec=True
MultipleEarlyAborts=True
AbortsStopMultiple=True
CoreCycles=True
HighExceptionVectors=True
ARM9Extensions=True
ARMv5PExtensions=True
ARM9OptimizedMemory=True
ARMJavaExtensions=False
ARMJavaV1Extensions=False
ARM9CoprocessorInterface=True
revision=2
; This revision is reflected in the "variant" field of CHIPID.
CHIPID=0x41259660
; If you put either of these to zero then it will be intepreted as
; 32 KB.  Zero IRam or DRam sizes are not useful configurations!
IRamSize=0x10000
DRamSize=0x10000
{DCC=Default_DebugComms
}
}

{ ARM968E-S-REV0=ARM966E-S-REV2
; We cannot yet model external TCRAM, or their timings,
; but we can model the internal 9-REV2 core.
{meta_moduleserver_processor=ARM968E-S
revision=0
}
Memory=ARM968E_S
Core=ARM9
ARMulator=ARM9ulator
Architecture=5T
Nexec=True
MultipleEarlyAborts=True
AbortsStopMultiple=True
CoreCycles=True
HighExceptionVectors=True
ARM9Extensions=True
ARMv5PExtensions=True
ARM9OptimizedMemory=True
ARMJavaExtensions=False
ARMJavaV1Extensions=False
ARM9CoprocessorInterface=True
revision=0
; This revision is reflected in the "variant" field of CHIPID.
CHIPID=0x41059680
; If you put either of these to zero then it will be intepreted as
; 32 KB.  Zero IRam or DRam sizes are not useful configurations!
IRamSize=0x10000
DRamSize=0x10000
{DCC=Default_DebugComms
}
}

{ ARM968E-S=ARM968E-S-REV0
}

{ ARM946E-S-REV1=Processors_Common_ARMULATE
CoprocessorInterfaceType=9
MODEL_DLL_FILENAME=armulate
{meta_moduleserver_processor=ARM946E-S
revision=1
}
Core=ARM9
ARMulator=ARM9ulator
Architecture=5T
Nexec=True
MultipleEarlyAborts=True
AbortsStopMultiple=True
CoreCycles=True
HighExceptionVectors=True
ARM9Extensions=True
ARM9CoprocessorInterface=True
ARMV5PEXTENSIONS=True
HASPU=True
CHIPID=0x41000000
REVISION=0x1
;This belongs to the memory.
;CHIPNUMBER=0x946
HASTCRAM=TRUE
HasSRAM=True
Memory=ARM946E_S
IRamSize=0x10000
DRamSize=0x10000
ICache_Associativity=4
DCache_Associativity=4

;; Use cache lines to change cache size
;; 512 = 16Kb